AD5204/AD5206
A6
W6
1
2
3
4
5
6
7
8
9
24 B4
23 W4
22 A4
21 B2
20 W2
19 A2
B6
GND
CS
AD5206
TOP VIEW
(Not to Scale)
V
DD
18
A1
SDI
17 W1
16 B1
15 A3
14 W3
13 B3
CLK
V
SS
B5 10
W5 11
A5 12
NC = NO CONNECT
Figure 8. AD5206 SOIC/TSSOP/PDIP Pin Configuration
Table 5. AD5206 Pin Function Descriptions
Pin No.
Name
Description
1
2
3
4
ꢀ
A6
W6
B6
GND
CS
Terminal A RDAC 6.
Wiper RDAC 6. Address = 1012.
Terminal B RDAC 6.
Ground.
Chip Select Input (Active Low). When CS returns high, data in the serial input register is decoded based on the
address bits, and then it is loaded into the target RDAC latch.
6
7
8
9
VDD
SDI
CLK
VSS
Bꢀ
Wꢀ
Aꢀ
B3
W3
A3
B1
W1
A1
A2
W2
B2
Positive Power Supply. This pin is specified for operation at both 3 V and ꢀ V. It is the sum of |VDD| + |VSS| < ꢀ.ꢀ V.
Serial Data Input. Data is input MSB first.
Serial Clock Input. This pin is positive edge triggered.
Negative Power Supply. This pin is specified for operation at both 0 V and −2.7 V. It is the sum of |VDD| + |VSS| < ꢀ.ꢀ V.
Terminal B RDAC ꢀ.
Wiper RDAC ꢀ. Address = 1002.
Terminal A RDAC ꢀ.
Terminal B RDAC 3.
Wiper RDAC 3. Address = 0102.
Terminal A RDAC 3.
Terminal B RDAC 1.
Wiper RDAC 1. Address = 0002.
Terminal A RDAC 1.
Terminal A RDAC 2.
Wiper RDAC 2. Address = 0012.
Terminal B RDAC 2.
Terminal A RDAC 4.
Wiper RDAC 4. Address = 0112.
Terminal B RDAC 4.
10
11
12
13
14
1ꢀ
16
17
18
19
20
21
22
23
24
A4
W4
B4
Rev. C | Page 9 of 20