AD5203
tap point located at 201 Ω [= RBA(nominal resistance)/64 + RW
= 156 Ω + 45 Ω)] for data 01H. The third connection is the next
tap point representing 312 + 45 = 357 Ω for data 02H. Each
LSB data value increase moves the wiper up the resistor ladder
until the last tap point is reached at 9889 Ω. The wiper does not
directly connect to the B Terminal. See Figure 34 for a simpli-
fied diagram of the equivalent RDAC circuit.
OPERATION
The AD5203 provides a quad channel, 64-position digitally-
controlled variable resistor (VR) device. Changing the pro-
grammed VR settings is accomplished by clocking in an 8-bit
serial data word into the SDI (Serial Data Input) pin. The for-
mat of this data word is two address bits, MSB first, followed by
six data bits, MSB first. Table I provides the serial register data
word format. The AD5203 has the following address assign-
ments for the ADDR decode, which determines the location of
VR latch receiving the serial register data in Bits B5 through B0:
The general transfer equation that determines the digitally pro-
grammed output resistance between Wx and Bx is:
R
WB(Dx) = (Dx)/64 × RBA + RW
(1)
VR# = A1 × 2 + A0 + 1
where Dx is the data contained in the 6-bit RDACx latch and
RBA is the nominal end-to-end resistance.
VR outputs can be changed one at a time in random sequence.
The serial clock running at 10 MHz makes it possible to load all
four VRs in under 3.2 µs (8 × 4 × 100 ns) for the AD5203. The
exact timing requirements are shown in Figure 1.
For example, when VB = 0 V and A–terminal is open circuit the
following output resistance values will be set for the following
RDAC latch codes (applies to the 10K potentiometer):
The AD5203 resets to a midscale by asserting the RS pin, sim-
plifying initial conditions at power-up. Both parts have a power
shutdown SHDN pin that places the RDAC in a zero power
consumption state where terminals Ax are open-circuited and
the wiper Wx is connected to Bx, resulting in only leakage cur-
rents being consumed in the VR structure. In shutdown mode
the VR latch settings are maintained so that, returning to opera-
tional mode from power shutdown, the VR settings return to
their previous resistance values.
D (DEC) RWB (⍀)
Output State
63
32
1
9889
5045
201
45
Full-Scale
Midscale (RS = 0 Condition)
1 LSB
0
Zero-Scale (Wiper Contact Resistance)
Note that in the zero-scale condition a finite wiper resistance of
45 Ω is present. Care should be taken to limit the current flow
between W and B in this state to a maximum value of 5 mA to
avoid degradation or possible destruction of the internal switch
contact.
Ax
R
S
SHDN
R
S
Like the mechanical potentiometer the RDAC replaces, it is
totally symmetrical. The resistance between the wiper W and
D5
D4
D3
D2
D1
D0
terminal A also produces a digitally controlled resistance RWA
.
R
S
When these terminals are used the B–terminal should be tied to
the wiper. Setting the resistance value for RWA starts at a maxi-
mum value of resistance and decreases as the data loaded in the
latch is increased in value. The general transfer equation for this
operation is:
Wx
RDAC
LATCH
&
DECODER
R
WA(Dx) = (64-Dx)/64 × RBA + RW
(2)
where Dx is the data contained in the 6-bit RDACx latch and
RBA is the nominal end-to-end resistance. For example, when
VA = 0 V and B–terminal is tied to the wiper W, the following
output resistance values will be set for the following RDAC
latch codes:
R
S
Bx
R
= R /64
AB
S
Figure 34. Equivalent RDAC Circuit
D (DEC)
RWA (⍀)
Output State
PROGRAMMING THE VARIABLE RESISTOR
Rheostat Operation
63
32
1
201
Full-Scale
Midscale (RS = 0 Condition)
1 LSB
5045
9889
10045
The nominal resistance of the RDAC between Terminals A and
B are available with values of 10 kΩ, and 100 kΩ. The final
digits of the part number determine the nominal resistance
value, e.g., 10 kΩ = 10; 100 kΩ = 100. The nominal resistance
(RAB) of the VR has 64 contact points accessed by the wiper
terminal, plus the B terminal contact. The 6-bit data word in
the RDAC latch is decoded to select one of the 64 possible
settings. The wiper’s first connection starts at the B terminal for
data 00H. This B–terminal connection has a wiper contact resis-
tance of 45 Ω. The second connection (10 kΩ part) is the first
0
Zero-Scale
The typical distribution of RBA from channel to channel matches
within ±1%. However, device-to-device matching is process-lot-
dependent, having a ±30% variation. The change in RBA with
temperature has a 700 ppm/°C temperature coefficient.
REV. 0
–9–
5秒后页面跳转
STM32H743技术深度剖析与应用案例探索
LM321中文资料解析：引脚功能介绍、技术特点、技术特性分析
74HC14芯片资料介绍：性能特性分析、引脚介绍
LM1875芯片手册：功放参数分析、引脚说明、电路设计要点
微信公众号
抖音公众号
浙公网安备 33010502006866号 浙ICP备10014259号-119
营业执照ICP证
技术参数
数据手册
如果您发现信息不准确，
