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AD5203AR100

更新时间： 2024-01-16 01:02:10
品牌 Logo 应用领域
罗彻斯特 - ROCHESTER 光电二极管转换器电阻器
页数 文件大小 规格书
13页 942K
描述
100K DIGITAL POTENTIOMETER, 3-WIRE SERIAL CONTROL INTERFACE, 64 POSITIONS, PDSO24, SOIC-24

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AD5203AR100 技术参数

是否无铅：含铅是否Rohs认证：不符合
生命周期：Active零件包装代码：SOIC
包装说明：SOP,针数：24
Reach Compliance Code：unknown风险等级：5.36
Is Samacsys：N其他特性：REST 3 RESISTOR ARRAY VALUES ARE : 10000OHMS
标称带宽：0.6 kHz控制接口：3-WIRE SERIAL
转换器类型：DIGITAL POTENTIOMETERJESD-30 代码：R-PDSO-G24
JESD-609代码：e0长度：15.4 mm
湿度敏感等级：1功能数量：1
位置数：64端子数量：24
最高工作温度：85 °C最低工作温度：-40 °C
封装主体材料：PLASTIC/EPOXY封装代码：SOP
封装形状：RECTANGULAR封装形式：SMALL OUTLINE
峰值回流温度（摄氏度）：240认证状态：COMMERCIAL
电阻定律：LINEAR最大电阻容差：30%
最大电阻器端电压：5.5 V最小电阻器端电压：
座面最大高度：2.65 mm标称供电电压：3 V
表面贴装：YES标称温度系数：700 ppm/ °C
温度等级：INDUSTRIAL端子面层：TIN LEAD
端子形式：GULL WING端子节距：1.27 mm
端子位置：DUAL处于峰值回流温度下的最长时间：30
标称总电阻：100000 Ω宽度：7.5 mm
Base Number Matches：1

AD5203AR100 数据手册

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AD5203  
PROGRAMMING THE POTENTIOMETER DIVIDER  
Voltage Output Operation  
The serial-data-output (SDO) pin contains an open drain  
n-channel FET. This output requires a pull-up resistor in order  
to transfer data to the next package’s SDI pin. The pull-up  
resistor termination voltage may be larger than the VDD supply  
of the AD5203 SDO output device, e.g., the AD5203 could  
operate at VDD = 3.3 V and the pull-up for interface to the next  
device could be set at +5 V. This allows for daisy chaining sev-  
eral RDACs from a single processor serial data line. Clock pe-  
riod needs to be increased when using a pull-up resistor to the  
SDI pin of the following device in the series. Capacitive loading  
at the daisy chain node SDO-SDI between devices must be  
accounted for to successfully transfer data. When daisy chaining  
is used, the CS should be kept low until all the bits of every  
package are clocked into their respective serial registers insuring  
that the address bits and data bits are in the proper decoding  
location. This would require 16 bits of address and data comply-  
ing to the word format provided in Table I if two AD5203 four-  
channel RDACs are daisy chained. During shutdown, SHDN  
the SDO output pin is forced to the off (logic high state) to  
disable power dissipation in the pull-up resistor. See Figure 37  
for equivalent SDO output circuit schematic.  
The digital potentiometer easily generates an output voltage  
proportional to the input voltage applied to a given terminal.  
For example connecting A–terminal to +5 V and B–terminal to  
ground produces an output voltage at the wiper which can be  
any value starting at zero volts up to 1 LSB less than +5 V.  
Each LSB of voltage is equal to the voltage applied across ter-  
minal AB divided by the 64 position resolution of the potenti-  
ometer divider. The general equation defining the output  
voltage with respect to ground for any given input voltage ap-  
plied to terminals AB is:  
VW(Dx) = Dx/64 × VAB + VB  
Operation of the digital potentiometer in the divider mode  
results in more accurate operation over temperature. Here the  
output voltage is dependent on the ratio of the internal resistors  
not the absolute value, therefore the drift improves to 20 ppm/°C.  
DIGITAL INTERFACING  
The AD5203 contains a standard three-wire serial input control  
interface. The three inputs are clock (CLK), CS and serial data  
input (SDI). The positive-edge sensitive CLK input requires  
clean transitions to avoid clocking incorrect data into the serial  
input register. Standard logic families work well. If mechanical  
switches are used for product evaluation they should be de-  
bounced by a flip-flop or other suitable means. The Figure 35  
block diagram shows more detail of the internal digital cir-  
cuitry. When CS is taken active low the clock loads data into  
the serial register on each positive clock edge, see Table III.  
Table II. Input Logic Control Truth Table  
CLK CS  
RS SHDN Register Activity  
L
P
L
L
H
H
H
H
No SR effect, enables SDO pin.  
Shift one bit in from the SDI pin.  
The eighth previously entered bit  
is shifted out of the SDO pin.  
Load SR data into RDAC latch  
based on A1, A0 decode (Table III).  
No Operation.  
Sets all RDAC latches to midscale,  
wiper centered and SDO latch  
cleared.  
X
P
H
H
X
X
H
X
H
L
H
H
AD5203  
V
CS  
DD  
A1  
W1  
B1  
CLK  
D5  
D0  
R
EN  
DAC  
LAT  
#1  
ADDR  
DEC  
X
X
H
H
P
H
H
L
Latches all RDAC latches to 20H.  
Open circuits all Resistor A–termi-  
nals, connects W to B, turns off  
SDO output transistor.  
A1  
A0  
DO  
SDO  
R
D5  
SER  
REG  
NOTE: P = positive edge, X = don’t care, SR = shift register.  
A4  
W4  
B4  
D5  
D0  
R
Table III. Address Decode Table  
DAC  
LAT  
#4  
DI  
SDI  
D0  
A1  
A0  
Latch Decoded  
6
R
0
0
1
1
0
1
0
1
RDAC#1  
RDAC#2  
RDAC#3  
RDAC#4  
SHDN  
AGND  
DGND  
RS  
Figure 35. Block Diagram  
–10–  
REV. 0  
1...8910111213

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