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AD5165BUJZ100-R2

更新时间： 2024-02-22 05:00:24
品牌 Logo 应用领域
亚德诺 - ADI 转换器数字电位计电阻器光电二极管
页数 文件大小 规格书
16页 575K
描述
256-Position, Ultralow Power 1.8 V Logic-Level Digital Potentiometer

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AD5165BUJZ100-R2 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Active零件包装代码：TSSOP
包装说明：VSSOP,针数：8
Reach Compliance Code：unknown风险等级：5.8
标称带宽：0.055 kHz控制接口：3-WIRE SERIAL
转换器类型：DIGITAL POTENTIOMETERJESD-30 代码：R-PDSO-G8
JESD-609代码：e3长度：2.9 mm
湿度敏感等级：1功能数量：1
位置数：256端子数量：8
最高工作温度：125 °C最低工作温度：-40 °C
封装主体材料：PLASTIC/EPOXY封装代码：VSSOP
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, VERY THIN PROFILE, SHRINK PITCH
峰值回流温度（摄氏度）：260认证状态：COMMERCIAL
电阻定律：LINEAR最大电阻容差：20%
最大电阻器端电压：3 V最小电阻器端电压：
座面最大高度：1 mm标称供电电压：3 V
表面贴装：YES标称温度系数：35 ppm/ °C
温度等级：AUTOMOTIVE端子面层：MATTE TIN
端子形式：GULL WING端子节距：0.65 mm
端子位置：DUAL处于峰值回流温度下的最长时间：40
标称总电阻：100000 Ω宽度：1.6 mm
Base Number Matches：1

AD5165BUJZ100-R2 数据手册

 浏览型号AD5165BUJZ100-R2的Datasheet PDF文件第10页浏览型号AD5165BUJZ100-R2的Datasheet PDF文件第11页浏览型号AD5165BUJZ100-R2的Datasheet PDF文件第12页浏览型号AD5165BUJZ100-R2的Datasheet PDF文件第13页浏览型号AD5165BUJZ100-R2的Datasheet PDF文件第15页浏览型号AD5165BUJZ100-R2的Datasheet PDF文件第16页 
AD5165  
The data setup and data hold times in the specifications table  
determine the valid timing requirements. The AD5165 uses an  
8-bit serial input data register word that is transferred to the  
internal RDAC register when the CS line returns to logic low.  
Extra MSB bits are ignored.  
PROGRAMMING THE POTENTIOMETER DIVIDER  
Voltage Output Operation  
The digital potentiometer easily generates a voltage divider at  
wiper-to-B and wiper-to-A proportional to the input voltage at  
A to B. Unlike the polarity of VDD to GND, which must be  
positive, voltage across A to B, W to A, and W to B can be at  
either polarity.  
ESD PROTECTION  
All digital inputs are protected with a series of input resistors  
and parallel Zener ESD structures, shown in Figure 39 and  
Figure 40. This applies to the digital input pins SDI, CLK,  
and CS.  
V
I
A
W
V
O
340Ω  
B
LOGIC  
Figure 38. Potentiometer Mode Configuration  
GND  
If ignoring the effect of the wiper resistance for approximation,  
connecting the A terminal to 5 V and the B terminal to ground  
produces an output voltage at the wiper-to-B starting at 0 V  
up to 1 LSB less than 5 V. Each LSB of voltage is equal to the  
voltage applied across terminals A and B divided by the 256  
positions of the potentiometer divider. The general equation  
defining the output voltage at VW with respect to ground for any  
valid input voltage applied to terminals A and B is  
Figure 39. ESD Protection of Digital Pins  
A, B, W  
GND  
Figure 40. ESD Protection of Resistor Terminals  
D
256  
256 − D  
256  
VW (D) =  
VA +  
VB  
(3)  
TERMINAL VOLTAGE OPERATING RANGE  
A more accurate calculation, which includes the effect of wiper  
resistance, VW, is  
The AD5165 VDD and GND power supply defines the boundary  
conditions for proper 3-terminal digital potentiometer oper-  
ation. Supply signals present on terminals A, B, and W that  
exceed VDD or GND are clamped by the internal forward-biased  
diodes, as shown in Figure 41.  
R
WB (D)  
RAB  
RWA(D)  
RAB  
(4)  
VW (D) =  
VA +  
VB  
V
DD  
Operation of the digital potentiometer in the divider mode  
results in a more accurate operation over temperature. Unlike  
the rheostat mode, the output voltage is dependent mainly on  
the ratio of the internal resistors RWA and RWB and not the  
absolute values. Therefore, the temperature drift reduces to  
15 ppm/°C.  
A
W
B
GND  
3-WIRE SERIAL BUS DIGITAL INTERFACE  
Figure 41. Maximum Terminal Voltages Set by VDD and GND  
The AD5165 contains a 3-wire digital interface (SDI, CS, and  
CLK). The 8-bit serial word must be loaded MSB first. The  
format of the word is shown in Table 5.  
POWER-UP SEQUENCE  
Because the ESD protection diodes limit the voltage compliance  
at terminals A, B, and W (see Figure 41), it is important to  
power VDD/GND before applying any voltage to terminals A, B,  
and W% otherwise, the diode is forward biased such that VDD is  
powered unintentionally and may affect the rest of the user’s  
circuit. The ideal power-up sequence is in the following order:  
GND, VDD, digital inputs, and then VA, VB, and VW. The relative  
order of powering VA, VB, VW, and the digital inputs is not  
important as long as they are powered after VDD/GND.  
The positive-edge sensitive CLK input requires clean transitions  
to avoid clocking incorrect data into the serial input register.  
Standard logic families work well. If mechanical switches are  
used for product evaluation, they should be debounced by a  
flip-flop or other suitable means. When CS is high, the clock  
loads data into the serial register on each positive clock edge,  
as shown in Figure 34.  
Rev. 0 | Page 14 of 16  
 
 
 
 
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