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AD5162BRMZ10 PDF预览

AD5162BRMZ10

更新时间： 2024-02-28 23:26:40
品牌 Logo 应用领域
亚德诺 - ADI 数字电位计
页数 文件大小 规格书
20页 830K
描述
Dual, 256-Position, SPI Digital Potentiometer

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AD5162BRMZ10 技术参数

是否无铅： 含铅是否Rohs认证： 符合
生命周期：Active零件包装代码：TSSOP
包装说明：TSSOP, TSSOP10,.19,20针数：10
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.39.00.01风险等级：1.7
其他特性：IT CAN ALSO OPERATE FROM 5 V NOMINAL SUPPLY标称带宽：0.6 kHz
控制接口：3-WIRE SERIAL转换器类型：DIGITAL POTENTIOMETER
JESD-30 代码：S-PDSO-G10JESD-609代码：e3
长度：3 mm湿度敏感等级：1
功能数量：2位置数：256
端子数量：10最高工作温度：125 °C
最低工作温度：-40 °C封装主体材料：PLASTIC/EPOXY
封装代码：TSSOP封装等效代码：TSSOP10,.19,20
封装形状：SQUARE封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度（摄氏度）：260电源：3/5 V
认证状态：Not Qualified电阻定律：LINEAR
最大电阻容差：20%最大电阻器端电压：5.5 V
最小电阻器端电压：座面最大高度：1.1 mm
子类别：Digital Potentiometers标称供电电压：3 V
表面贴装：YES技术：CMOS
标称温度系数：35 ppm/ °C温度等级：AUTOMOTIVE
端子面层：Matte Tin (Sn)端子形式：GULL WING
端子节距：0.5 mm端子位置：DUAL
处于峰值回流温度下的最长时间：30标称总电阻：10000 Ω
宽度：3 mmBase Number Matches：1

AD5162BRMZ10 数据手册

 浏览型号AD5162BRMZ10的Datasheet PDF文件第11页浏览型号AD5162BRMZ10的Datasheet PDF文件第12页浏览型号AD5162BRMZ10的Datasheet PDF文件第13页浏览型号AD5162BRMZ10的Datasheet PDF文件第15页浏览型号AD5162BRMZ10的Datasheet PDF文件第16页浏览型号AD5162BRMZ10的Datasheet PDF文件第17页 
AD5162  
PROGRAMMING THE POTENTIOMETER DIVIDER  
ESD PROTECTION  
Voltage Output Operation  
All digital inputs are protected with a series of input resistors  
and parallel Zener ESD structures, as shown in Figure 36 and  
The digital potentiometer easily generates a voltage divider at  
wiper to B and wiper to A, proportional to the input voltage at  
A to B. Unlike the polarity of VDD to GND, which must be  
positive, voltage across A to B, W to A, and W to B can be at  
either polarity.  
CS  
Figure 37. This applies to the SDI, CLK, and  
digital input pins.  
340Ω  
LOGIC  
GND  
V
I
A
Figure 36. ESD Protection of Digital Pins  
A, B, W  
W
V
O
B
GND  
Figure 35. Potentiometer Mode Configuration  
Figure 37. ESD Protection of Resistor Terminals  
If ignoring the effect of the wiper resistance for approximation,  
connecting the A terminal to 5 V and the B terminal to ground  
produces an output voltage at the wiper to B, starting at 0 V up  
to 1 LSB less than 5 V. Each LSB of voltage is equal to the voltage  
applied across the A and B terminals divided by the 256 positions  
of the potentiometer divider. The general equation defining the  
output voltage at VW with respect to ground for any valid input  
voltage applied to Terminal A and Terminal B is  
TERMINAL VOLTAGE OPERATING RANGE  
The AD5162 VDD and GND power supply defines the boundary  
conditions for proper 3-terminal digital potentiometer opera-  
tion. Supply signals present on the A, B, and W terminals that  
exceed VDD or GND are clamped by the internal forward-biased  
diodes (see Figure 38).  
V
DD  
D
256  
256 − D  
256  
A
VW (D) =  
VA +  
VB  
(3)  
W
B
A more accurate calculation, which includes the effect of wiper  
resistance, VW, is  
GND  
R
WB(D)  
RAB  
RWA(D)  
RAB  
VW (D) =  
VA +  
VB  
(4)  
Figure 38. Maximum Terminal Voltages Set by VDD and GND  
Operation of the digital potentiometer in the divider mode  
POWER-UP SEQUENCE  
results in more accurate operation over temperature. Unlike in  
the rheostat mode, the output voltage is dependent mainly on  
the ratio of the internal resistors RWA and RWB, not on the absolute  
values. Therefore, the temperature drift reduces to 15 ppm/°C.  
Because the ESD protection diodes limit the voltage compliance  
at the A, B, and W terminals (see Figure 38), it is important to  
power VDD/GND before applying voltage to the A, B, and W  
terminals; otherwise, the diode is forward-biased such that VDD  
is powered unintentionally and may affect the rest of the user’s  
circuit. The ideal power-up sequence is in the following order:  
GND, VDD, digital inputs, and then VA, VB, VW. The relative  
order of powering VA, VB, VW, and the digital inputs is not  
important, as long as they are powered after VDD/GND.  
Rev. C | Page 14 of 20  
 
 
 
 
 
 
 
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