Datasheet > AD5160BRJ5

AD5160BRJ5

更新时间： 2024-01-28 19:31:21

品牌	Logo	应用领域
亚德诺 - ADI		光电二极管转换器电阻器
页数	文件大小	规格书
16页	409K
描述
IC 5K DIGITAL POTENTIOMETER, 3-WIRE SERIAL CONTROL INTERFACE, 256 POSITIONS, PDSO8, 2.90 X 3 MM, PLASTIC, MO-178BA, SOT-23, 8 PIN, Digital Potentiometer

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AD5160BRJ5 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
零件包装代码：	SOIC	包装说明：	LSSOP, TSSOP8,.1
针数：	8	Reach Compliance Code：	not_compliant
ECCN代码：	EAR99	HTS代码：	8542.39.00.01
风险等级：	5.35	其他特性：	IT CAN ALSO OPERATE FROM A 5V NOMINAL SUPPLY
标称带宽：	1.2 kHz	控制接口：	3-WIRE SERIAL
转换器类型：	DIGITAL POTENTIOMETER	JESD-30 代码：	R-PDSO-G8
JESD-609代码：	e0	长度：	2.9 mm
功能数量：	1	位置数：	256
端子数量：	8	最高工作温度：	125 °C
最低工作温度：	-40 °C	封装主体材料：	PLASTIC/EPOXY
封装代码：	LSSOP	封装等效代码：	TSSOP8,.1
封装形状：	RECTANGULAR	封装形式：	SMALL OUTLINE, LOW PROFILE, SHRINK PITCH
峰值回流温度（摄氏度）：	220	电源：	3/5 V
认证状态：	Not Qualified	电阻定律：	LINEAR
最大电阻容差：	30%	最大电阻器端电压：	3 V
最小电阻器端电压：		座面最大高度：	1.45 mm
子类别：	Digital Potentiometers	标称供电电压：	3 V
表面贴装：	YES	技术：	CMOS
标称温度系数：	45 ppm/ °C	温度等级：	AUTOMOTIVE
端子面层：	Tin/Lead (Sn/Pb)	端子形式：	GULL WING
端子节距：	0.65 mm	端子位置：	DUAL
处于峰值回流温度下的最长时间：	30	标称总电阻：	5000 Ω
宽度：	1.6 mm	Base Number Matches：	1

AD5160BRJ5 数据手册

AD5160

PROGRAMMING THE POTENTIOMETER DIVIDER

ESD PROTECTION

Voltage Output Operation

All digital inputs are protected with a series input resistor and

parallel Zener ESD structures are shown in Figure 40 and

The digital potentiometer easily generates a voltage divider at

wiper-to-B and wiper-to-A proportional to the input voltage at

A-to-B. Unlike the polarity of V_DDto GND, which must be

positive, voltage across A to B, W to A, and W to B can be at

either polarity.

Figure 41. This applies to SDI, CLK, and , which are the

digital input pins.

340Ω

LOGIC

GND

If ignoring the effect of the wiper resistance for approximation,

connecting the A terminal to 5 V and the B terminal to ground

produces an output voltage at the wiper-to-B starting at 0 V up

to 1 LSB less than 5 V. Each LSB of voltage is equal to the

voltage applied across Terminal A and Terminal B divided by

the 256 positions of the potentiometer divider. The general

equation defining the output voltage at V_Wwith respect to

ground for any valid input voltage applied to Terminal A and

Terminal B is

Figure 40. ESD Protection of Digital Pins

A,B,W

GND

Figure 41. ESD Protection of Resistor Terminals

POWER-UP SEQUENCE

Because the ESD protection diodes limit the voltage compliance

at the A, B, and W terminals, it is important to power V_DD/GND

before applying any voltage to the A, B, and W terminals;

otherwise, the diode forward biases such that V_DDis powered

unintentionally and may affect the rest of the user’s circuit. The

ideal power-up sequence is in the following order: GND, V_DD,

digital inputs, and then V_A/B/W. The relative order of powering

V_A, V_B, V_W, and the digital inputs is not important as long as

they are powered after V_DD/GND.

256

256 − D

256

V_W(D) =

V_A

V_B

(3)

For a more accurate calculation, which includes the effect of

wiper resistance, V_Wcan be found as

_WB(D)

256

_WA(D)

256

V_W(D) =

V_A

V_B

(4)

Operation of the digital potentiometer in the divider mode

results in a more accurate operation over temperature. Unlike

the rheostat mode, the output voltage is dependent mainly on

the ratio of the internal resistors (R_WAand R_WB) and not the

absolute values. Therefore, the temperature drift reduces to

15 ppm/°C.

LAYOUT AND POWER SUPPLY BYPASSING

It is a good practice to employ compact, minimum lead length

layout design. Keep the leads to the inputs as direct as possible

with a minimum conductor length. Ground paths should have

low resistance and low inductance.

Similarly, it is also a good practice to bypass the power supplies

with quality capacitors for optimum stability. Bypass supply

leads to the device with disc or chip ceramic capacitors of

0.01 μF to 0.1 μF. To minimize any transient disturbance and

low frequency ripple, apply low ESR 1 μF to 10 μF tantalum or

electrolytic capacitors at the supplies (see Figure 42). To

minimize the ground bounce, join the digital ground remotely

to the analog ground at a single point.

SPI-COMPATIBLE 3-WIRE SERIAL BUS

The AD5160 contains a 3-wire SPI-compatible digital interface

(SDI, , and CLK). The 8-bit serial word must be loaded MSB

first. The format of the word is shown in Table 6.

The positive-edge sensitive CLK input requires clean transitions

to avoid clocking incorrect data into the serial input register.

Standard logic families work well. If mechanical switches are

used for product evaluation, they should be debounced by a

flip-flop or other suitable means. When

is low, the clock

loads data into the serial register on each positive clock edge

(see Figure 37).

10μF

0.1μF

AD5160

The data setup and data hold times in the specification table

determine the valid timing requirements. The AD5160 uses an

8-bit serial input data register word that is transferred to the

GND

internal RDAC register when the

Extra MSB bits are ignored.

line returns to logic high.

Figure 42. Power Supply Bypassing

Rev. B | Page 15 of 16

1...12 13 141516

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