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AD5160BRJ100-RL7 PDF预览

AD5160BRJ100-RL7

更新时间： 2024-02-12 01:06:19
品牌 Logo 应用领域
亚德诺 - ADI 转换器数字电位计电阻器光电二极管
页数 文件大小 规格书
16页 775K
描述
256-Position SPI Compatible Digital Potentiometer

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AD5160BRJ100-RL7 技术参数

是否无铅： 不含铅是否Rohs认证： 不符合
生命周期：Obsolete零件包装代码：SOIC
包装说明：2.90 X 3 MM, MO-178BA, SOT-23, 8 PIN针数：8
Reach Compliance Code：not_compliantECCN代码：EAR99
HTS代码：8542.39.00.01风险等级：5.34
Is Samacsys：N其他特性：IT CAN ALSO OPERATE FROM A 5V NOMINAL SUPPLY
标称带宽：0.04 kHz控制接口：3-WIRE SERIAL
转换器类型：DIGITAL POTENTIOMETERJESD-30 代码：R-PDSO-G8
JESD-609代码：e0长度：2.9 mm
湿度敏感等级：1功能数量：1
位置数：256端子数量：8
最高工作温度：125 °C最低工作温度：-40 °C
封装主体材料：PLASTIC/EPOXY封装代码：LSSOP
封装等效代码：TSSOP8,.1封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, LOW PROFILE, SHRINK PITCH峰值回流温度（摄氏度）：NOT SPECIFIED
电源：3/5 V认证状态：Not Qualified
电阻定律：LINEAR最大电阻容差：30%
最大电阻器端电压：3 V最小电阻器端电压：
座面最大高度：1.45 mm子类别：Digital Potentiometers
标称供电电压：3 V表面贴装：YES
标称温度系数：45 ppm/ °C温度等级：AUTOMOTIVE
端子面层：Tin/Lead (Sn85Pb15)端子形式：GULL WING
端子节距：0.65 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED标称总电阻：100000 Ω
宽度：1.6 mmBase Number Matches：1

AD5160BRJ100-RL7 数据手册

 浏览型号AD5160BRJ100-RL7的Datasheet PDF文件第10页浏览型号AD5160BRJ100-RL7的Datasheet PDF文件第11页浏览型号AD5160BRJ100-RL7的Datasheet PDF文件第12页浏览型号AD5160BRJ100-RL7的Datasheet PDF文件第14页浏览型号AD5160BRJ100-RL7的Datasheet PDF文件第15页浏览型号AD5160BRJ100-RL7的Datasheet PDF文件第16页 
AD5160  
PROGRAMMING THE POTENTIOMETER DIVIDER  
Voltage Output Operation  
ESD PROTECTION  
All digital inputs are protected with a series input resistor and  
parallel Zener ESD structures shown in Figure 39 and Figure 40.  
This applies to the digital input pins SDI, CLK, and  
The digital potentiometer easily generates a voltage divider at  
wiper-to-B and wiper-to-A proportional to the input voltage at  
A-to-B. Unlike the polarity of VDD to GND, which must be  
positive, voltage across A-B, W-A, and W-B can be at either  
polarity.  
CS  
.
340Ω  
LOGIC  
V
SS  
If ignoring the effect of the wiper resistance for approximation,  
connecting the A terminal to 5 V and the B terminal to ground  
produces an output voltage at the wiper-to-B starting at 0 V up  
to 1 LSB less than 5 V. Each LSB of voltage is equal to the  
voltage applied across terminal AB divided by the 256 positions  
of the potentiometer divider. The general equation defining the  
output voltage at VW with respect to ground for any valid input  
voltage applied to terminals A and B is  
Figure 39. ESD Protection of Digital Pins  
A,B,W  
V
SS  
Figure 40. ESD Protection of Resistor Terminals  
D
256  
256 − D  
256  
VW (D) =  
VA  
+
VB  
(3)  
TERMINAL VOLTAGE OPERATING RANGE  
The AD5160 VDD and GND power supply defines the boundary  
conditions for proper 3-terminal digital potentiometer  
operation. Supply signals present on terminals A, B, and W that  
exceed VDD or GND will be clamped by the internal forward  
biased diodes (see Figure 41).  
For a more accurate calculation, which includes the effect of  
wiper resistance, VW, can be found as  
RWB (D)  
256  
RWA (D)  
256  
VW (D) =  
VA  
+
VB  
(4)  
V
DD  
Operation of the digital potentiometer in the divider mode  
results in a more accurate operation over temperature. Unlike  
the rheostat mode, the output voltage is dependent mainly on  
the ratio of the internal resistors RWA and RWB and not the  
absolute values. Therefore, the temperature drift reduces to  
15 ppm/°C.  
A
W
B
V
SS  
Figure 41. Maximum Terminal Voltages Set by VDD and VSS  
SPI COMPATIBLE 3-WIRE SERIAL BUS  
The AD5160 contains a 3-wire SPI compatible digital interface  
CS  
(SDI, , and CLK). The 8-bit serial word must be loaded MSB  
POWER-UP SEQUENCE  
first. The format of the word is shown in Table 5.  
Since the ESD protection diodes limit the voltage compliance at  
terminals A, B, and W (see Figure 41), it is important to power  
VDD/GND before applying any voltage to terminals A, B, and Wꢀ  
otherwise, the diode will be forward biased such that VDD will be  
powered unintentionally and may affect the rest of the user’s  
circuit. The ideal power-up sequence is in the following order:  
GND, VDD, digital inputs, and then VA/B/W. The relative order of  
powering VA, VB, VW, and the digital inputs is not important as  
long as they are powered after VDD/GND.  
The positive-edge sensitive CLK input requires clean transitions  
to avoid clocking incorrect data into the serial input register.  
Standard logic families work well. If mechanical switches are  
used for product evaluation, they should be debounced by a  
CS  
flip-flop or other suitable means. When  
is low, the clock  
loads data into the serial register on each positive clock edge  
(see Figure 36).  
The data setup and data hold times in the specification table  
determine the valid timing requirements. The AD5160 uses an  
8-bit serial input data register word that is transferred to the  
CS  
internal RDAC register when the  
Extra MSB bits are ignored.  
line returns to logic high.  
Rev. 0 | Page 13 of 16  
 
 
 
 
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