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AD5065BRUZ-1 PDF预览

AD5065BRUZ-1

更新时间： 2024-02-14 10:19:19
品牌 Logo 应用领域
亚德诺 - ADI 转换器数模转换器光电二极管
页数 文件大小 规格书
33页 755K
描述
Fully Accurate 12-/14-/16-Bit VOUT DAC SPI Interface 2.7 V to 5.5 V in a TSSOP

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AD5065BRUZ-1 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Obsolete零件包装代码：TSSOP
包装说明：TSSOP, TSSOP14,.25针数：14
Reach Compliance Code：compliant风险等级：5.75
Is Samacsys：N最大模拟输出电压：5 V
最小模拟输出电压：转换器类型：D/A CONVERTER
输入位码：BINARY输入格式：SERIAL
JESD-30 代码：R-PDSO-G14JESD-609代码：e3
长度：5 mm最大线性误差 (EL)：0.0023%
位数：16功能数量：2
端子数量：14最高工作温度：125 °C
最低工作温度：-40 °C封装主体材料：PLASTIC/EPOXY
封装代码：TSSOP封装等效代码：TSSOP14,.25
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度（摄氏度）：260电源：3/5 V
认证状态：Not Qualified座面最大高度：1.2 mm
标称安定时间 (tstl)：14 µs子类别：Other Converters
最大压摆率：4 mA标称供电电压：5 V
表面贴装：YES温度等级：AUTOMOTIVE
端子面层：MATTE TIN端子形式：GULL WING
端子节距：0.65 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：4.4 mm
Base Number Matches：1

AD5065BRUZ-1 数据手册

 浏览型号AD5065BRUZ-1的Datasheet PDF文件第27页浏览型号AD5065BRUZ-1的Datasheet PDF文件第28页浏览型号AD5065BRUZ-1的Datasheet PDF文件第29页浏览型号AD5065BRUZ-1的Datasheet PDF文件第31页浏览型号AD5065BRUZ-1的Datasheet PDF文件第32页浏览型号AD5065BRUZ-1的Datasheet PDF文件第33页 
AD5025/45/65  
Preliminary Technical Data  
serial write operation is performed to the DAC. PC7 is taken  
high at the end of this procedure.  
MICROPROCESSOR INTERFACING  
AD5025/45/65 to Blackfin® ADSP-BF53X Interface  
AD5024/44/64 to 80C51/80L51 Interface  
Figure 48 shows a serial interface between the AD5025/45/65  
and the Blackfin ADSP-BF53X microprocessor. The ADSP-  
BF53X processor family incorporates two dual-channel  
synchronous serial ports, SPORT1 and SPORT0, for serial and  
multiprocessor communications. Using SPORT0 to connect to  
the AD5025/45/65, the setup for the interface is as follows:  
DT0PRI drives the DIN pin of the AD5025/45/65, while  
Figure 50 shows a serial interface between the AD5024/44/64  
and the 80C51/80L51 microcontroller. The setup for the  
interface is as follows: TxD of the 80C51/ 80L51 drives SCLK of  
the AD5025/45/65, and RxD drives the serial data line of the  
SYNC  
part. The  
signal is again derived from a bit-programmable  
pin on the port. In this case, Port Line P3.3 is used. When data is  
to be transmitted to the AD5025/45/65, P3.3 is taken low. The  
80C51/80L51 transmit data in 8-bit bytes only; thus, only eight  
falling clock edges occur in the transmit cycle. To load data to  
the DAC, P3.3 is left low after the first eight bits are transmitted,  
and a second write cycle is initiated to transmit the second byte  
of data. P3.3 is taken high following the completion of this  
cycle. The 80C51/80L51 output the serial data in a format that  
has the LSB first. The AD5025/45/65 must receive data with the  
MSB first. The 80C51/80L51 transmit routine should take this  
into account.  
SYNC  
TSCLK0 drives the SCLK of the parts. The  
TFS0.  
is driven from  
AD5065/  
AD5045/  
AD5025  
1
ADSP-BF53x  
1
TFS0  
DTOPRI  
TSCLK0  
SYNC  
DIN  
SCLK  
1
ADDITIONAL PINS OMITTED FOR CLARITY.  
AD5065/  
1
80C51/80L51  
AD5045/  
AD5025  
SYNC  
Figure 48. AD5025/45/65 to Blackfin ADSP-BF53X Interface  
1
P3.3  
TxD  
RxD  
AD5025/45/65 to 68HC11/68L11 Interface  
Figure 49 shows a serial interface between the AD5025/45/65  
and the 68HC11/68L11 microcontroller. SCK of the  
68HC11/68L11 drives the SCLK of the AD5025/45/65, and the  
MOSI output drives the serial data line of the DAC.  
SCLK  
DIN  
1
ADDITIONAL PINS OMITTED FOR CLARITY.  
Figure 50. AD5025/45/65 to 80C512/80L51 Interface  
AD5065/  
AD5045/  
AD5025/  
1
68HC11/68L11  
1
AD5025/45/65 to MICROWIRE Interface  
PC7  
SCK  
SYNC  
SCLK  
DIN  
Figure 51 shows an interface between the AD5025/45/65 and any  
MICROWIRE-compatible device. Serial data is shifted out on the  
falling edge of the serial clock and is clocked into the  
MOSI  
AD5025/45/65 on the rising edge of the SCLK.  
1
ADDITIONAL PINS OMITTED FOR CLARITY.  
Figure 49. AD5025/45/65 to 68HC11/68L11 Interface  
AD5065/  
1
MICROWIRE  
AD5045/  
1
AD5025  
SYNC  
CS  
SK  
SO  
SYNC  
The  
signal is derived from a port line (PC7). The setup  
DIN  
conditions for correct operation of this interface are as follows:  
The 68HC11/68L11 is configured with its CPOL bit as 0, and its  
CPHA bit as 1. When data is being transmitted to the DAC, the  
SCLK  
SYNC  
line is taken low (PC7). When the 68HC11/ 68L11 is  
1
ADDITIONAL PINS OMITTED FOR CLARITY.  
configured as described previously, data appearing on the MOSI  
output is valid on the falling edge of SCK. Serial data from the  
68HC11/68L11 is transmitted in 8-bit bytes with only eight  
falling clock edges occurring in the transmit cycle. Data is  
transmitted MSB first. To load data to the AD5025/45/65, PC7  
is left low after the first eight bits are transferred, and a second  
Figure 51. AD5025/45/654 to MICROWIRE Interface  
Rev. PrB | Page 30 of 33  
1...27282930313233

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