AD5025/45/65
Preliminary Technical Data
updates synchronously; that is, the DAC register is updated
CLEAR CODE REGISTER
after new data is read, regardless of the state of the
pin.
LDAC
The AD5025/45/65 has a hardware
asynchronous clear input. The
pin that is an
input is falling edge
CLR
It effectively sees the
pin as being tied low. (See Table 15
LDAC
CLR
for the
register mode of operation.) This flexibility is
LDAC
sensitive. Bringing the
line low clears the contents of the
CLR
input register and the DAC registers to the data contained in the
user-configurable register and sets the analog outputs
useful in applications where the user wants to simultaneously
update select channels while the rest of the channels are
synchronously updating.
CLR
accordingly. (see Table 13) This function can be used in system
calibration to load zero scale, midscale, or full scale to all
channels together. These clear code values are user-
programmable by setting two bits, Bit DB1 and Bit DB0, in the
control register (see Table 13). The default setting clears the
outputs to 0 V. Command 0101 is reserved for loading the clear
code register (see Table 7).
Writing to the DAC using command 0110 loads the 4-bit
LDAC
register (DB3 to DB0). The default for each channel is 0; that is,
the pin works normally. Setting the bits to 1 means the
LDAC
DAC channel is updated regardless of the state of the
LDAC
pin. See Table 16 for the contents of the input shift register
during the load register mode of operation.
LDAC
The part exits clear code mode on the 32nd falling edge of the
POWER SUPPLY BYPASSING AND GROUNDING
next write to the part. If
is activated during a write
CLR
When accuracy is important in a circuit, it is helpful to carefully
consider the power supply and ground return layout on the
board. The printed circuit board containing the AD5666 should
have separate analog and digital sections. If the AD5666 is in a
system where other devices require an AGND-to-DGND
connection, the connection should be made at one point only.
This ground point should be as close as possible to the
AD5025/45/65.
sequence, the write is aborted.
The pulse activation time—the falling edge of
to when
CLR
CLR
the output starts to change—is typically TBD ns. However, if
outside the DAC linear region, it typically takes TBD ns after
executing
for the output to start changing (see Figure 38).
CLR
See Table 14 for contents of the input shift register during the
loading clear code register operation
The power supply to the AD5025/45/65 should be bypassed with
10 μF and 0.1 μF capacitors. The capacitors should physically be
as close as possible to the device, with the 0.1 μF capacitor
ideally right up against the device. The 10 μF capacitors are the
tantalum bead type. It is important that the 0.1 μF capacitor has
low effective series resistance (ESR) and low effective series
inductance (ESI), such as is typical of common ceramic types of
capacitors. This 0.1 μF capacitor provides a low impedance path
to ground for high frequencies caused by transient currents due
to internal logic switching.
FUNCTION
LDAC
The outputs of all DACs can be updated simultaneously using
the hardware
pin.
LDAC
Synchronous
: After new data is read, the DAC registers
LDAC
are updated on the falling edge of the 32nd SCLK pulse.
can be permanently low or pulsed as in Figure 3
LDAC
Asynchronous
: The outputs are not updated at the same
LDAC
time that the input registers are written to. When
low, the DAC registers are updated with the contents of the
input register.
goes
LDAC
The power supply line should have as large a trace as possible to
provide a low impedance path and reduce glitch effects on the
supply line. Clocks and other fast switching digital signals
should be shielded from other parts of the board by digital
ground. Avoid crossover of digital and analog signals if possible.
When traces cross on opposite sides of the board, ensure that
they run at right angles to each other to reduce feedthrough
effects through the board. The best board layout technique is
the microstrip technique, where the component side of the
board is dedicated to the ground plane only and the signal
traces are placed on the solder side. However, this is not always
possible with a 2-layer board.
Alternatively, the outputs of all DACs can be updated
simultaneously using the software
function by writing to
LDAC
Input Register n and updating all DAC registers. Command
0010 is reserved for this software function.
LDAC
register gives the user extra flexibility and control
An
LDAC
over the hardware
pin. This register allows the user to
LDAC
select which combination of channels to simultaneously update
when the hardware pin is executed. Setting the bit
LDAC
register to 0 for a DAC channel means that this channel’s update
is controlled by the pin. If this bit is set to 1, this channel
LDAC
LDAC
Rev. PrB | Page 28 of 33
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