Datasheet > AD4680BCPZ-RL7

AD4680BCPZ-RL7

更新时间： 2022-05-14 22:21:38

品牌	Logo	应用领域
亚德诺 - ADI		/
页数	文件大小	规格书
29页	427K
描述
Differential Inputs, 1 MSPS/500 kSPS, Dual Simultaneous Sampling SAR ADCs

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AD4680BCPZ-RL7 数据手册

Data Sheet

AD4680/AD4681

TIMING SPECIFICATIONS

V_CC= 3.0 V to 3.6 V, V_LOGIC= 1.65 V to 3.6 V, V_REF= 2.5 V internal, and T_A= −40°C to +125°C, unless otherwise noted.

Table 3.

Parameter Min

Typ

Max

Unit Description

Time between conversions

AD4680

t_CYC

μs

AD4681

t_SCLKED

t_SCLK

t_SCLKH

t_SCLKL

t_CSH

190

CS falling edge to first SCLK falling edge

SCLK period

SCLK high time

SCLK low time

CS pulse width

t_QUIET

Interface quiet time prior to conversion

500

1500

t_SDOEN

CS low to SDOA and SDOB/ALERT enabled

V_LOGIC≥ 2.25 V

1.65 V ≤ V_LOGIC< 2.25 V

SCLK rising edge to SDOA and SDOB/ALERT hold time

SCLK rising edge to SDOA and SDOB/ALERT setup time

V_LOGIC≥ 2.25 V

t_SDOH

t_SDOS

1.65 V ≤ V_LOGIC< 2.25 V

t_SDOT

CS rising edge to SDOA and SDOB/ALERT high impedance

SDI setup time prior to SCLK falling edge

SDI hold time after SCLK falling edge

SCLK rising edge to CS rising edge

Conversion time

t_SDIS

t_SDIH

t_SCLKCS

t_CONVERT

t_ACQUIRE

190

Acquire time

810

1800

AD4680

AD4681

t_RESET

Valid time to start conversion after software reset (see Figure 37)

Valid time to start conversion after soft reset

Valid time to start conversion after hard reset

Supply active to conversion

250

800

t_POWERUP

First conversion allowed

Settled to within 1% with internal reference

Settled to within 1% with external reference

Supply active to register read write access allowed

Exiting shutdown mode to conversion

Settled to within 1% with internal reference

Settled to within 1% with external reference

Time from CS to ALERT indication (see Figure 36)

Time from CS to ALERT clear (see Figure 36)

t_REGWRITE

t_STARTUP

200

μs

t_ALERTS

t_ALERTC

Rev. 0 | Page 5 of 29

1 2 3 456 7 8...29

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