MODEL: AD3V
MDF.
CODE
ITEM
P/L
DATA
CONTENTS
DEFAULT
----
N/A
-9999 – 9999 Output display in engineering unit with ITEM 01 DATA 1 (as set in ITEM 06/07)
(-FFFF – FFFF) Loop test output with ITEM 01 DATA 2 (‘L’ is indicated as ITEM No.)
BCD or binary (with polarity), offset binary, two’s complement, reected binary
01
1, 2, 3
Modication code
1 : Data indication only.
2 : All parameters are modiable.
3 : Only ITEM 24 is modiable.
1
02
03
N/A
N/A
0 – 99
Status indication (“0” is normally indicated.)
0: Normal 1: Memory error 10: Out of input range -15 – +115%
0
-15.0 – 115.0 Input indicated in % (of the range set in ITEM 22/23)
----
04
05
06
07
06
07
06
07
06
07
06
07
08
2
2
2
2
2
2
2
2
2
2
2
2
2
-99.99 – 99.99 Zero adjustment (%) (ne adj. of the value set in ITEM 22)
-99.99 – 99.99 Span adjustment (%) (ne adj. of the value set in ITEM 23)
0.00
0.00
-9999 – 9999 BCD
-9999 – 9999
Display range scaling 0% *1
Display range scaling 100% *1
Display range scaling 0% *1
Display range scaling 100% *1
Display range scaling 0% *1
Display range scaling 100% *1
Display range scaling 0% *1
Display range scaling 100% *1
Display range scaling 0% *1
Display range scaling 100% *1
-1000
1000
-7FFF
7FFF
0000
FFFF
8000
7FFF
0000
FFFF
5
-7FFF – 7FFF Binary
-7FFF – 7FFF
0000 – FFFF Offset binary
0000 – FFFF
8000 – 7FFF Two’s complement
8000 – 7FFF
0000 – FFFF Reected binary
0000 – FFFF
0 – 99
Power ON-delay time (seconds)
09
2
0, 1, 2, 3, 4
Display code 0 : BCD with polarity (decimal)
1 : Binary with polarity 2 : Offset binary
0
3 : Two’s complement
4 : Reected binary
10
11
12
2
2
2
0, 1, 2, 3, 4
0, 1, 2
Available number of bits
0: 16 bits 1: 14 bits 2: 12 bits 3: 10 bits 4: 8 bits
Parity check
0
0
0
0: Disable 1: Enable Parity per each digit 2: Enable Parity for all digits
Odd or even parity (Checking the number of High in the output)
0 : Odd (CMOS level, open collector (PNP) ),
Even (open collector (NPN) )
0, 1
1 : Even (CMOS level, open collector (PNP) ),
Odd (open collector (NPN) )
13
14
2
2
0, 1
0, 1
POL, OVF output logic 0 : Data available at High (CMOS level) or ON (open collector)
1 : Data available at Low (CMOS level) or OFF (open collector)
0
0
Data output logic *2
0 : Positive (CMOS level, open collector (PNP) ),
Negative (open collector (NPN) )
1 : Negative (CMOS level, open collector (PNP) ),
Positive (open collector (NPN) )
15
16
2
2
0, 1
0, 1
HOLD input logic
DAV output logic
0 : HOLD at Low or shortcircuit
1 : HOLD at High or open circuit
0
0
0 : Data available at High (CMOS level) or ON (open collector)
1 : Data available at Low (CMOS level) or OFF (open collector)
17
18
2
2
1 – 50
DAV output time (msec.) selectable up to 50% of the Output Rate (ITEM 20)
1
1
0, 1, 2, 3, 4, 5 Moving average (10 msec./sampling)
0: No 1: 5 samples 2: 8 samples 3: 12 samples 4: 20 samples 5: 36 samples
Delay buffer (seconds, 0 – 90%)
19
2
0.0 – 60.0
0.5
* When setting to less than or equal to 0.1, response time is 0.15 seconds.
20
21
2
2
1 – 20
Output rate ‘n’ ratio (n : 1 – 20 times)
1
0, 1 – 60
Power-saving mode
Input code S1
Input code S2
Input code S3
Input code Z1
0 : Continuous display
1 – 60 : Time before display turned off (minutes)
0% input voltage (V) *3
100% input voltage (V) *3
0% input voltage (V) *3
100% input voltage (V) *3
0% input voltage (V) *3
100% input voltage (V) *3
0% input current (mA) *3
100% input current (mA) *3
10
22
23
22
23
22
23
22
23
24
2
2
2
2
2
2
2
2
3
-1.00 – 1.00
-1.00 – 1.00
-10.0 – 10.0
-10.0 – 10.0
-30.0 – 30.0
-30.0 – 30.0
0.0 – 50.0
0.0 – 50.0
0, 1
-1.00
1.00
-10.0
10.0
-30.0
30.0
4.0
20.0
0
Reset all settings
ROM version
25
N/A
----
----
*1. Of the range set in ITEM 04/05. ITEM 06 < ITEM 07.
*2. ITEM 13, 15 or 16 is independent from ITEM 14.
*3. ITEM 22 < ITEM 23.
AD3V SPECIFICATIONS
ES-1389 Rev.24 Page 4/9
https://www.m-system.co.jp/
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