Datasheet > AD261AND-5

AD261AND-5

更新时间： 2024-01-05 01:25:19

品牌	Logo	应用领域
亚德诺 - ADI		/
页数	文件大小	规格书
6页	186K
描述
High Speed, Logic Isolator

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技术参数
数据手册

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AD261AND-5 技术参数

是否无铅：	含铅	是否Rohs认证：	不符合
生命周期：	Active	零件包装代码：	QIP
包装说明：	QIP,	针数：	22/16
Reach Compliance Code：	unknown	风险等级：	5.59
JESD-30 代码：	R-PQIP-T16	湿度敏感等级：	NOT SPECIFIED
I/O 线路数量：	5	端口数量：	1
端子数量：	16	最高工作温度：	85 °C
最低工作温度：	-25 °C	封装主体材料：	PLASTIC/EPOXY
封装代码：	QIP	封装形状：	RECTANGULAR
封装形式：	IN-LINE	峰值回流温度（摄氏度）：	NOT SPECIFIED
认证状态：	COMMERCIAL	座面最大高度：	11.18 mm
最大供电电压：	5.75 V	最小供电电压：	4 V
标称供电电压：	5 V	表面贴装：	NO
温度等级：	OTHER	端子面层：	NOT SPECIFIED
端子形式：	THROUGH-HOLE	端子节距：	2.54 mm
端子位置：	QUAD	处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	11.43 mm	uPs/uCs/外围集成电路类型：	PARALLEL IO PORT, GENERAL PURPOSE
Base Number Matches：	1

AD261AND-5 数据手册

AD261

SCHMITT

TRIGGER

BUFFER

3.5kV

ISOLATION

BARRIER

Logic information is sent across the barrier as “set-hi/set-lo”

data that is derived from logic level transitions of the input. At

power-up or after a fault condition, an output might not repre-

sent the state of the respective channel input to the isolator. An

internal circuit operates in the background which interrogates

all inputs about every 5 µs and in the absence of logic transi-

tions, sends appropriate “set-hi” or “set-lo” data across the

barrier.

DATA

RECEIVER BUFFER

OUTPUT

DRIVER

OUT

DATA IN

ENABLE

D Q

ENABLE

CONTINUOUS

UPDATE CIRCUIT

GATED

TRANSPARENT

LATCH

Figure 1. Sim plified Block Diagram

Recovery time from a fault condition or at power-up is thus

between 5 µs and 10 µs.

POSITIVE GOING

INPUT THRESHOLD

HYSTERESIS

NEGATIVE GOING

INPUT

INPUT THRESHOLD

63%

OUTPUT

37%

t_ff

PROPAGATION DELAY

t_PD= 14ns

DELAY LINE

14ns

BUFFER

EFFECTIVE

CIRCUIT

MODEL

100⍀

5pF

INPUT

5pF

OUTPUT

CAPACITANCE

t_rr

= t_ff= 100⍀ x C

TOTAL OUTPUT CAPACITANCE

0.5ns – NO LOAD

= 5.5ns INTO 50pF

TOTAL DELAY = t_PDt_rr= 13ns (NO LOAD), 18ns (50pF LOAD)

Figure 2. Typical Tim ing and Delay Models

O UTLINE D IMENSIO NS

D imensions shown in inches and (mm).

22-P in P lastic D IP

(ND -22A)

0.550 (13.97)

1.500 (38.1) MAX

MAX

0.440

(11.18)

MAX

END VIEW

SIDE VIEW

0.100

(2.54)

0.350

(8.89)

0.050 (1.27)

PIN 1

0.160 (4.06)

0.140 (3.56)

0.020

0.010

(0.508

0.254)

16 PLACES

0.075 (1.91)

BOTTOM

VIEW

SYSTEM

0.250

(6.35)

0.738* (18.75)

FIELD

0.050

(1.27)

0.650 (16.51)

*CREEPAGE PATH (SUBTRACT APPROXIMATELY

0.079 (2mm) FOR SOLDER PAD RADII ON PC BOARD.

THIS SPACING SUPPORTS THE INTRINSICALLY SAFE

RATING OF 750V.

–6–

REV. 0

1...3 4 56

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