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AD261AND-5

更新时间： 2024-01-02 02:45:56
品牌 Logo 应用领域
亚德诺 - ADI /
页数 文件大小 规格书
6页 186K
描述
High Speed, Logic Isolator

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AD261AND-5 技术参数

是否无铅： 含铅是否Rohs认证： 不符合
生命周期：Active零件包装代码：QIP
包装说明：QIP,针数：22/16
Reach Compliance Code：unknown风险等级：5.59
JESD-30 代码：R-PQIP-T16湿度敏感等级：NOT SPECIFIED
I/O 线路数量：5端口数量：1
端子数量：16最高工作温度：85 °C
最低工作温度：-25 °C封装主体材料：PLASTIC/EPOXY
封装代码：QIP封装形状：RECTANGULAR
封装形式：IN-LINE峰值回流温度（摄氏度）：NOT SPECIFIED
认证状态：COMMERCIAL座面最大高度：11.18 mm
最大供电电压：5.75 V最小供电电压：4 V
标称供电电压：5 V表面贴装：NO
温度等级：OTHER端子面层：NOT SPECIFIED
端子形式：THROUGH-HOLE端子节距：2.54 mm
端子位置：QUAD处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：11.43 mmuPs/uCs/外围集成电路类型：PARALLEL IO PORT, GENERAL PURPOSE
Base Number Matches：1

AD261AND-5 数据手册

 浏览型号AD261AND-5的Datasheet PDF文件第1页浏览型号AD261AND-5的Datasheet PDF文件第2页浏览型号AD261AND-5的Datasheet PDF文件第3页浏览型号AD261AND-5的Datasheet PDF文件第4页浏览型号AD261AND-5的Datasheet PDF文件第6页 
AD261  
AD 261 CO NFIGURATIO NS  
AD261-4  
AD261-5  
LATCH  
D
LATCH  
F0  
F1  
F2  
F3  
F4  
F0  
D
LINE 0  
LINE 1  
LINE 0  
LINE 1  
S0  
S0  
E
E
LATCH  
LATCH  
D
F1  
F2  
F3  
F4  
S1  
D
E
2
3
4
5
2
3
4
5
S1  
S2  
S3  
E
LATCH  
LATCH  
D
E
D
E
S2  
S3  
S4  
LINE 2  
LINE 3  
LINE 4  
LINE 2  
LINE 3  
LINE 4  
LATCH  
LATCH  
D
E
D
E
LATCH  
D
LATCH  
D
E
S4  
E
ENABLE  
+5V dc  
ENABLE  
+5V dc  
17  
6
ENABLE  
17  
6
ENABLE  
+5V dc  
SYS  
SYS  
FLD  
FLD  
+5V dc  
+5V dc  
+5V dc  
+5V dc  
+5V dc  
5V RTN  
16  
15  
7
8
16  
15  
7
8
FLD  
FLD  
SYS  
SYS  
5V dc RTN  
5V dc RTN  
5V dc RTN  
5V dc RTN  
5V RTN  
5V RTN  
5V RTN  
SYS  
FLD  
SYS  
FLD  
FIELD  
FIELD  
SYSTEM  
SYSTEM  
(Continued from page 1)  
GENERAL ATTRIBUTES  
T he AD261 provides five HCMOS compatible isolated logic  
lines with ≥ 10 kV/µs common-mode transient immunity.  
Field a nd System Ena ble Functions: Both the isolated and  
nonisolated sides of the AD261 have ENABLE pins that three-  
state all outputs. Upon reenabling these pins, all outputs are  
updated to reflect the current input logic level.  
T he case design and pin arrangement provides greater than  
18 mm spacing between field and system side conductors, pro-  
viding CSA/IS and IEC creepage spacing consistent with 750 V  
mains isolation.  
CE Cer tifia ble: Simply by adding the external bypass capacitors  
at the supply pins, the AD261 can attain CE certification in  
most applications (to the EMC directive) and conformance to  
the low voltage (safety) directive is assured by the EN60950  
certification.  
T he five unidirectional logic lines have six possible combina-  
tions of “ins” and “outs,” or transmitter/receiver pairs; hence  
there are six AD261 part configurations (see T able I).  
Each 20 MHz logic line has a Schmidt trigger input and a three-  
state output (on the other side of the isolation barrier) and 14 ns of  
propagation delay. A single enable pin on either side of the  
barrier causes all outputs on that side to go three-state and all  
inputs (driven pins) to ignore their inputs and retain their last  
known state.  
Table I. Model Num ber and P inout Function  
P in AD 261-0  
AD 261-1 AD 261-2 AD 261-3 AD 261-4 AD 261-5  
1
2
3
4
5
6
7
8
S0 (Xmt)  
S1 (Xmt)  
S2 (Xmt)  
S3 (Xmt)  
S4 (Xmt)  
ENABLESYS  
+5 V dcSYS  
5 V RT NSYS  
S0 (Xmt) S0 (Xmt) S0 (Xmt) S0 (Xmt) S0 (Rcv)  
S1 (Xmt) S1 (Xmt) S1 (Xmt) S1 (Rcv) S1 (Rcv)  
S2 (Xmt) S2 (Xmt) S2 (Rcv) S2 (Rcv) S2 (Rcv)  
S3 (Xmt) S3 (Rcv) S3 (Rcv) S3 (Rcv) S3 (Rcv)  
S4 (Rcv) S4 (Rcv) S4 (Rcv) S4 (Rcv) S4 (Rcv)  
Note: All unused logic inputs (1–5) should be tied either high or low,  
but not left floating.  
Edge “fidelity,” or the difference in propagation time for rising  
and falling edges, is typically less than ±1 ns.  
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
Power consumption, unlike opto-isolators, is a function of operat-  
ing frequency. Each logic line barrier driver requires about 160 µA  
per MHz and each receiver 40 µA per MHz plus, of course, 4 mA  
total idle current (each side). T he supply current diminishes  
slightly with increasing temperature (about –0.03%/°C).  
9–14  
15  
16  
17  
18  
19  
20  
21  
22  
Not Present  
5 V RTNFLD  
+5 V dcFLD  
ENABLEFLD  
F0 (Rcv)  
F1 (Rcv)  
F2 (Rcv)  
*
*
*
*
*
*
*
*
*
*
*
*
*
*
F0 (Rcv) F0 (Rcv) F0 (Rcv) F0 (Rcv) F0 (Xmt)  
F1 (Rcv) F1 (Rcv) F1 (Rcv) F1 (Xmt) F1 (Xmt)  
F2 (Rcv) F2 (Rcv) F2 (Xmt) F2 (Xmt) F2 (Xmt)  
F3 (Rcv) F3 (Xmt) F3 (Xmt) F3 (Xmt) F3 (Xmt)  
F4 (Xmt) F4 (Xmt) F4 (Xmt) F4 (Xmt) F4 (Xmt)  
T he total capacitance spanning the isolation barrier is less than  
10 pF.  
F3 (Rcv)  
F4 (Rcv)  
T he minimum period of a pulse that can be accurately coupled  
across the barrier is about 25 ns. T herefore the maximum  
square-wave frequency of operation is 20 MHz.  
*Pin function is the same on all models, as shown in the AD261-0 column.  
REV. 0  
–5–  
123456

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