AD1853JRSZ

更新时间： 2024-02-21 05:48:00

品牌	Logo	应用领域
亚德诺 - ADI		/
页数	文件大小	规格书
16页	358K
描述
Stereo, 24-Bit, 192 kHz, Multibit DAC

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数据手册

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AD1853JRSZ 技术参数

是否无铅：	不含铅	是否Rohs认证：	符合
生命周期：	Active	零件包装代码：	SSOP
包装说明：	SSOP,	针数：	28
Reach Compliance Code：	unknown	风险等级：	5.31
商用集成电路类型：	CONSUMER CIRCUIT	JESD-30 代码：	R-PDSO-G28
JESD-609代码：	e3	长度：	10.21 mm
湿度敏感等级：	1	功能数量：	1
端子数量：	28	最高工作温度：	70 °C
最低工作温度：		封装主体材料：	PLASTIC/EPOXY
封装代码：	SSOP	封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE, SHRINK PITCH	峰值回流温度（摄氏度）：	260
认证状态：	COMMERCIAL	座面最大高度：	1.98 mm
最大供电电压 (Vsup)：	5.5 V	最小供电电压 (Vsup)：	4.5 V
表面贴装：	YES	温度等级：	COMMERCIAL
端子面层：	MATTE TIN	端子形式：	GULL WING
端子节距：	0.65 mm	端子位置：	DUAL
处于峰值回流温度下的最长时间：	40	宽度：	5.295 mm

AD1853JRSZ 数据手册

AD1853

Table III. Digital Timing

Min

Units

t_CCH

t_CCL

t_CSU

t_CHD

t_CLL

t_CLH

CCLK HI Pulsewidth

CCLK LOW Pulsewidth

CDATA Setup Time

CDATA Hold Time

CLATCH LOW Pulsewidth

CLATCH HI Pulsewidth

SPI REGISTER DEFINITIONS

VOLUME LEFT and VOLUME RIGHT Registers

The SPI port allows flexible control of many chip parameters.

It is organized around three registers; a LEFT-CHANNEL

VOLUME register, a RIGHT-CHANNEL VOLUME register

and a CONTROL register. Each WRITE operation to the

AD1853 SPI control port requires 16 bits of serial data in

MSB-first format. The bottom two bits are used to select one

of three registers, and the top 14 bits are then written to that

single 16-bit transaction.

A write operation to the left or right volume registers will acti-

vate the “auto-ramp” clickless volume control feature of the

AD1853. This feature works as follows. The upper 10 bits of

the volume control word will be incremented or decremented by

1 at a rate equal to the input sample rate. The bottom 4 bits are

not fed into the auto-ramp circuit and thus take effect immedi-

ately. This arrangement gives a worst-case ramp time of about

1024/F_Sfor step changes of more than 60 dB, which has been

determined by listening tests to be optimal in terms of pre-

venting the perception of a “click” sound on large volume

changes. See Figure 8 for a graphical description of how the

volume changes as a function of time.

The SPI CCLK signal is used to clock in the data. The incom-

ing data should change on the falling edge of this signal. At the

end of the 16 CCLK periods, the CLATCH signal should rise

to latch the data internally into the AD1853.

The 14-bit volume control word is used to multiply the signal,

and therefore the control characteristic is linear, not dB. A con-

stant dB/step characteristic can be obtained by using a lookup

table in the microprocessor that is writing to the SPI port.

The lowest two bits of the 16-bit input word are decoded as

follows to set the register into which the upper 14 bits will be

written.

Bit 1

Bit 0

VOLUME REQUEST REGISTER

Volume Left

Volume Right

Control Register

–60

ACTUAL VOLUME REGISTER

–60

TIME

20ms

Figure 8. Smooth Volume Control

REV. A

–9–

1...6 7 8910 11 12...16

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