AD1853JRSZ

更新时间： 2024-02-23 12:56:50

品牌	Logo	应用领域
亚德诺 - ADI		/
页数	文件大小	规格书
16页	358K
描述
Stereo, 24-Bit, 192 kHz, Multibit DAC

阅读下载

获取价格

技术参数
数据手册

如果您发现信息不准确，欢迎纠错

AD1853JRSZ 技术参数

是否无铅：	不含铅	是否Rohs认证：	符合
生命周期：	Active	零件包装代码：	SSOP
包装说明：	SSOP,	针数：	28
Reach Compliance Code：	unknown	风险等级：	5.31
商用集成电路类型：	CONSUMER CIRCUIT	JESD-30 代码：	R-PDSO-G28
JESD-609代码：	e3	长度：	10.21 mm
湿度敏感等级：	1	功能数量：	1
端子数量：	28	最高工作温度：	70 °C
最低工作温度：		封装主体材料：	PLASTIC/EPOXY
封装代码：	SSOP	封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE, SHRINK PITCH	峰值回流温度（摄氏度）：	260
认证状态：	COMMERCIAL	座面最大高度：	1.98 mm
最大供电电压 (Vsup)：	5.5 V	最小供电电压 (Vsup)：	4.5 V
表面贴装：	YES	温度等级：	COMMERCIAL
端子面层：	MATTE TIN	端子形式：	GULL WING
端子节距：	0.65 mm	端子位置：	DUAL
处于峰值回流温度下的最长时间：	40	宽度：	5.295 mm

AD1853JRSZ 数据手册

AD1853

Figure 1 shows the right-justified mode. LRCLK is HI for the

left channel, LO for the right channel. Data is valid on the rising

edge of BCLK.

OPERATING FEATURES

Serial Data Input Port

The AD1853’s flexible serial data input port accepts data in

twos-complement, MSB-first format. The left channel data field

always precedes the right channel data field. The serial mode is

set by using either the external mode pins (IDPM0 Pin 21 and

IDPM1 Pin 20) or the mode select bits (Bits 4 and 5) in the SPI

control register. To control the serial mode using the external

mode pins, the SPI mode select bits should be set to zero

(default at power-up). To control the serial mode using the SPI

mode select bits, the external mode control pins should be

grounded.

In normal operation, there are 64-bit clocks per frame (or 32

per half-frame). When the SPI word length control bits (Bits 8

and 9 in the control register) are set to 24 bits (0:0), the serial

port will begin to accept data starting at the 8th bit clock pulse

after the L/RCLK transition. When the word length control bits

are set to 20-bit mode, data is accepted starting at the 12th bit

clock position. In 16-bit mode, data is accepted starting at the

16th-bit clock position. These delays are independent of the

number of bit clocks per frame, and therefore other data formats

are possible using the delay values described above. For detailed

timing, see Figure 6.

Figure 2 shows the I²S mode. L/RCLK is LO for the left chan-

nel, and HI for the right channel. Data is valid on the rising

edge of BCLK. The MSB is left-justified to an L/RCLK transi-

tion but with a single BCLK period delay. The I²S mode can be

used to accept any number of bits up to 24.

In all modes except for the right-justified mode, the serial port

will accept an arbitrary number of bits up to a limit of 24 (extra

bits will not cause an error, but they will be truncated inter-

nally). In the right-justified mode, control register Bits 8 and 9

are used to set the word length to 16, 20, or 24 bits. The default

on power-up is 24-bit mode. When the SPI Control Port is not

being used, the SPI pins (3, 4 and 5) should be tied LO.

Serial Data Input Mode

The AD1853 uses two multiplexed input pins to control the

mode configuration of the input data port mode.

Figure 3 shows the left-justified mode. L/RCLK is HI for the

left channel, and LO for the right channel. Data is valid on the

rising edge of BCLK. The MSB is left-justified to an L/RCLK

transition, with no MSB delay. The left-justified mode can

accept any word length up to 24 bits.

Table I. Serial Data Input Modes

Figure 4 shows the DSP serial port mode. L/RCLK must pulse

HI for at least one bit clock period before the MSB of the left

channel is valid, and L/RCLK must pulse HI again for at least

one bit clock period before the MSB of the right channel is

valid. Data is valid on the falling edge of BCLK. The DSP serial

port mode can be used with any word length up to 24 bits.

IDPM1

(Pin 20)

IDPM0

(Pin 21)

Serial Data Input Format

Right Justified (24 Bits) Default

I²S-Compatible

Left Justified

DSP

t_DBH

t_DBP

BCLK

t_DBL

t_DLS

L/RCLK

t_DDS

MSB

SDATA

LEFT-JUSTIFIED

MSB-1

MODE

t_DDH

t_DDS

MSB

t_DDH

SDATA

I S-JUSTIFIED

MODE

t_DDS

LSB

t_DDH

t_DDS

MSB

t_DDH

SDATA

RIGHT-JUSTIFIED

MODE

8-BIT CLOCKS

(24-BIT DATA)

12-BIT CLOCKS

(20-BIT DATA)

16-BIT CLOCKS

(16-BIT DATA)

Figure 6. Serial Data Port Timing

REV. A

–7–

1...4 5 678 9 10...16

下载PDF

与AD1853JRSZ相关器件

型号	品牌	描述	获取价格	数据表
AD1854	ADI	Stereo, 96 kHz, Multibit DAC	获取价格
AD1854JRS	ADI	Stereo, 96 kHz, Multibit DAC	获取价格
AD1854JRSRL	ADI	Stereo, 96 kHz, Multibit DAC	获取价格
AD1854JRSZ	ADI	Stereo, 96 kHz, Multibit Sigma-Delta DAC	获取价格
AD1854JRSZRL	ADI	Stereo, 96 kHz, Multibit Sigma-Delta DAC	获取价格
AD1854KRS	ADI	Stereo, 96 kHz, Multibit DAC	获取价格

与AD1853JRSZ相关文章

STM32F030C6芯片介绍：主要参数分析、引脚配置说明、功耗及封装
2024-05-11

9
PCF8591数据手册解读：参数、引脚说明
2024-05-11

13
一文带你了解ss8050参数、引脚配置、应用指南
2024-05-11

7
深入解析AD7606高性能多通道模数转换器：资料手册参数分析
2024-05-10

9

产品中心

服务支持

精选活动

关于我们

帮助中心

AD1853JRSZ

AD1853JRSZ 技术参数

AD1853JRSZ 数据手册

与AD1853JRSZ相关器件

与AD1853JRSZ相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

AD1853JRSZ

AD1853JRSZ 技术参数

AD1853JRSZ 数据手册

与AD1853JRSZ相关器件

与AD1853JRSZ相关文章

您还可以找

您在本页遇到什么问题？