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AD1853JRSZ PDF预览

AD1853JRSZ

更新时间： 2024-02-08 14:30:10
品牌 Logo 应用领域
亚德诺 - ADI /
页数 文件大小 规格书
16页 358K
描述
Stereo, 24-Bit, 192 kHz, Multibit  DAC

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AD1853JRSZ 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Active零件包装代码：SSOP
包装说明：SSOP,针数：28
Reach Compliance Code：unknown风险等级：5.31
商用集成电路类型：CONSUMER CIRCUITJESD-30 代码：R-PDSO-G28
JESD-609代码：e3长度：10.21 mm
湿度敏感等级：1功能数量：1
端子数量：28最高工作温度：70 °C
最低工作温度：封装主体材料：PLASTIC/EPOXY
封装代码：SSOP封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, SHRINK PITCH峰值回流温度（摄氏度）：260
认证状态：COMMERCIAL座面最大高度：1.98 mm
最大供电电压 (Vsup)：5.5 V最小供电电压 (Vsup)：4.5 V
表面贴装：YES温度等级：COMMERCIAL
端子面层：MATTE TIN端子形式：GULL WING
端子节距：0.65 mm端子位置：DUAL
处于峰值回流温度下的最长时间：40宽度：5.295 mm

AD1853JRSZ 数据手册

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AD1853  
PIN FUNCTION DESCRIPTIONS  
Pin  
Input/Output  
Pin Name  
Description  
Digital Ground.  
1
2
I
I
DGND  
MCLK  
Master Clock Input. Connect to an external clock source. See Table II for allowable  
frequencies.  
3
4
I
I
CLATCH  
CCLK  
Latch input for control data. This input is rising-edge sensitive.  
Control clock input for control data. Control input data must be valid on the rising edge  
of CCLK. CCLK may be continuous or gated.  
5
6
7
8
9
I
CDATA  
INT4×  
Serial control input, MSB first, containing 16 bits of unsigned data. Used for specifying  
control information and channel-specific attenuation.  
Assert HI to select interpolation ratio of 4×, for use with double-speed inputs (88 kHz or  
96 kHz). Assert LO to select 8× interpolation ratio.  
Assert HI to select interpolation ratio of 2×, for quad-speed inputs (176 kHz or 192 kHz).  
Assert LO to select 8× interpolation ratio.  
Right Channel Zero Flag Output. This pin goes HI when Right Channel has no signal  
input for more than 1024 LR Clock Cycles.  
De-Emphasis. Digital de-emphasis is enabled when this input signal is HI. This is used to  
impose a 50 µs/15 µs response characteristic on the output audio spectrum at an assumed  
44.1 kHz sample rate. Curves for 32 kHz and 48 kHz sample rates may be selected via  
SPI control register.  
I
I
INT2×  
O
I
ZEROR  
DEEMP  
10  
11  
12  
13  
14  
I
I
O
O
O
IREF  
Connection point for external bias resistor. Voltage held at VREF  
Analog Ground.  
Left Channel Positive line level analog output.  
Left Channel Negative line level analog output.  
Voltage Reference Filter Capacitor Connection. Bypass and decouple the voltage refer-  
.
AGND  
OUTL+  
OUTL–  
FILTR  
ence with parallel 10 µF and 0.1 µF capacitors to the AGND (Pin 11).  
15  
16  
17  
18  
19  
20  
21  
22  
I
FCR  
Filter cap return pin for cap connected to FILTB (Pin 19).  
Right Channel Negative line level analog output.  
Right Channel Positive line level analog output.  
Analog Power Supply. Connect to analog +5 V supply.  
Filter Capacitor connection, connect 10 µF capacitor to FCR (Pin 15).  
Input serial data port mode control one. With IDPM0, defines one of four serial modes.  
Input serial data port mode control zero. With IDPM1, defines one of four serial modes.  
Left Channel Zero Flag output. This pin goes HI when Left Channel has no signal input  
for more than 1024 LR Clock Cycles.  
O
O
I
O
I
OUTR–  
OUTR+  
AVDD  
FILTB  
IDPM1  
IDPM0  
ZEROL  
I
O
23  
24  
I
I
MUTE  
RST  
Mute. Assert HI to mute both stereo analog outputs. Deassert LO for normal operation.  
Reset. The AD1853 is placed in a reset state when this pin is held LO. The AD1853 is  
reset on the rising edge of this signal. The serial control port registers are reset to the  
default values. Connect HI for normal operation.  
25  
26  
27  
I
I
I
L/RCLK  
BCLK  
SDATA  
Left/Right clock input for input data. Must run continuously.  
Bit clock input for input data.  
Serial input, MSB first, containing two channels of 16/18/20/24 bit twos-complement  
data.  
28  
I
DVDD  
Digital Power Supply Connect to digital +5 V supply.  
REV. A  
–5–  
12345678...16

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