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AD1833AST

更新时间： 2024-01-16 22:43:54
品牌 Logo 应用领域
亚德诺 - ADI /
页数 文件大小 规格书
20页 407K
描述
Multichannel 24-Bit, 192 kHz, DAC

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中文翻译

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AD1833AST 技术参数

是否无铅： 含铅是否Rohs认证： 不符合
生命周期：Active零件包装代码：QFP
包装说明：LFQFP,针数：48
Reach Compliance Code：unknown风险等级：5.77
转换器类型：D/A CONVERTER输入位码：2'S COMPLEMENT
输入格式：SERIALJESD-30 代码：S-PQFP-G48
JESD-609代码：e0长度：7 mm
湿度敏感等级：NOT SPECIFIED位数：24
功能数量：1端子数量：48
最高工作温度：85 °C最低工作温度：-40 °C
封装主体材料：PLASTIC/EPOXY封装代码：LFQFP
封装形状：SQUARE封装形式：FLATPACK, LOW PROFILE, FINE PITCH
峰值回流温度（摄氏度）：NOT SPECIFIED认证状态：COMMERCIAL
座面最大高度：1.6 mm标称供电电压：5 V
表面贴装：YES温度等级：INDUSTRIAL
端子面层：TIN LEAD端子形式：GULL WING
端子节距：0.5 mm端子位置：QUAD
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：7 mm
Base Number Matches：1

AD1833AST 数据手册

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AD1833  
Packed Mode 128  
Packed Mode 256  
In Packed Mode 128, all six data channels are “packed” into  
one sample interval on one data pin. The BCLK runs at 128 ×  
fS; therefore there are 128 BCLK periods in each sample inter-  
val. Each sample interval is broken into eight time slots, six slots  
of 20 BCLKs and two of four BCLKs. The data length is restricted  
in this mode to a maximum of 20 bits. The three left channels  
are written first, MSB first, and the data is written on the falling  
edge of BCLK. After the three left channels are written, there is  
a space of four BCLKs and then the three right channels are  
written. The L/RCLK defines the left and right data transmis-  
sion; it is high for the three left channels and low for the three  
right channels.  
In Packed Mode 256 all six data channels are “packed” into one  
sample interval on one data pin. The BCLK runs at 256 × fS;  
therefore there are 256 BCLK periods in each sample interval.  
Each sample interval is broken into eight time slots of 32 BCLKs  
each. The data length can be 16, 20, or 24 bits. The three left  
channels are written first, MSB first, and the data is written on  
the falling edge of BCLK with a one BCLK period delay from  
the start of the slot. After the three left channels are written,  
there is a space of 32 BCLKs and then the three right channels  
are written. The L/RCLK defines the left and right data trans-  
mission; it is low for the three left channels and high for the  
three right channels.  
L/RCLK  
BCLK  
SLOT 1  
LEFT 0  
BLANK SLOT  
4 SCLKs  
SLOT 2  
LEFT 1  
SLOT 3  
LEFT 2  
SLOT 4  
RIGHT 0  
BLANK SLOT  
4 SCLKs  
SLOT 5  
RIGHT 1  
SLOT 6  
RIGHT 2  
DATA  
BCLK  
MSB  
MSB MSB  
–2 –3  
MSB  
LSB  
+4  
LSB  
+3  
LSB  
+2  
LSB  
+1  
MSB  
MSB  
20-BIT DATA  
16-BIT DATA  
LSB  
–1  
–4  
MSB  
MSB MSB  
–2 –3  
MSB  
LSB  
–1  
–4  
Figure 9. Packed Mode 128  
L/RCLK  
BCLK  
DATA  
SLOT 1  
LEFT 0  
SLOT 2  
LEFT 1  
SLOT 3  
LEFT 2  
SLOT 4  
RIGHT 0  
SLOT 5  
RIGHT 1  
SLOT 6  
RIGHT 2  
BCLK  
MSB  
MSB MSB  
MSB  
LSB  
+8  
LSB  
+7  
LSB  
+6  
LSB  
+5  
LSB  
+4  
LSB  
+3  
LSB  
+2  
LSB  
+1  
MSB  
MSB  
MSB  
LSB  
24-BIT DATA  
20-BIT DATA  
16-BIT DATA  
–1  
–2  
–3  
–4  
MSB  
MSB MSB  
–2 –3  
MSB  
LSB  
+4  
LSB  
+3  
LSB  
+2  
LSB  
+1  
LSB  
–1  
–4  
MSB  
MSB MSB  
–2 –3  
MSB  
LSB  
–1  
–4  
Figure 10. Packed Mode 256  
–14–  
REV. 0  
1...11121314151617...20

中文翻译

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