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AD10265/PCB

更新时间： 2024-02-21 09:41:46
品牌 Logo 应用领域
亚德诺 - ADI 转换器
页数 文件大小 规格书
18页 270K
描述
Dual Channel, 12-Bit, 65 MSPS A/D Converter with Analog Input Signal Conditioning

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AD10265/PCB 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：QFP包装说明：CERAMIC, LCC-68
针数：68Reach Compliance Code：not_compliant
ECCN代码：EAR99HTS代码：8542.39.00.01
风险等级：5.89最大模拟输入电压：2 V
最小模拟输入电压：-2 V转换器类型：ADC, PROPRIETARY METHOD
JESD-30 代码：S-CQFP-G68JESD-609代码：e0
长度：24.13 mm标称负供电电压：-5 V
模拟输入通道数量：3位数：12
功能数量：2端子数量：68
最高工作温度：125 °C最低工作温度：-55 °C
输出位码：2'S COMPLEMENT BINARY输出格式：PARALLEL, WORD
封装主体材料：CERAMIC, METAL-SEALED COFIRED封装代码：QFP
封装等效代码：QFP68,1.2SQ,50封装形状：SQUARE
封装形式：FLATPACK峰值回流温度（摄氏度）：220
电源：+-5 V认证状态：Not Qualified
采样速率：65 MHz采样并保持/跟踪并保持：TRACK
子类别：Analog to Digital Converters标称供电电压：5 V
表面贴装：YES技术：BIPOLAR
温度等级：MILITARY端子面层：Tin/Lead (Sn/Pb)
端子形式：GULL WING端子节距：1.27 mm
端子位置：QUAD处于峰值回流温度下的最长时间：30
宽度：24.13 mmBase Number Matches：1

AD10265/PCB 数据手册

 浏览型号AD10265/PCB的Datasheet PDF文件第1页浏览型号AD10265/PCB的Datasheet PDF文件第2页浏览型号AD10265/PCB的Datasheet PDF文件第4页浏览型号AD10265/PCB的Datasheet PDF文件第5页浏览型号AD10265/PCB的Datasheet PDF文件第6页浏览型号AD10265/PCB的Datasheet PDF文件第7页 
AD10265  
Test  
Level  
Mil  
Subgroup  
AD10265AZ  
Typ  
Parameter  
Temp  
Min  
Max  
Units  
SPURIOUS-FREE DYNAMIC RANGE9  
Analog Input @ 1.24 MHz  
+25°C  
Full  
+25°C  
Full  
+25°C  
Full  
I
II  
I
II  
I
II  
4
5, 6  
4
5, 6  
4
5, 6  
75  
75  
72  
72  
72  
72  
80  
80  
80  
79  
79  
79  
dBFS  
dBFS  
dBFS  
dBFS  
dBFS  
dBFS  
@ 17 MHz  
@ 32 MHz  
TWO-TONE IMD REJECTION10  
f1, f2 @ –7 dBFS  
Full  
II  
4, 5, 6  
12  
72  
80  
80  
dBc  
dB  
CHANNEL-TO-CHANNEL ISOLATION11  
+25°C  
IV  
LINEARITY  
Differential Nonlinearity  
(Encode = 20 MHz)  
Integral Nonlinearity  
(Encode = 20 MHz)  
+25°C  
IV  
V
12  
–1.0  
±0.5  
1.5  
0.5  
LSB  
LSB  
Full  
±1.25  
DIGITAL OUTPUTS  
Logic Compatibility  
Logic “1” Voltage  
Logic “0” Voltage  
Output Coding  
CMOS  
DVCC – 0.2  
0.2  
Full  
Full  
I
I
1, 2, 3  
1, 2, 3  
2.8  
V
V
Twos Complement  
POWER SUPPLY  
AVCC Supply Voltage  
I (AVCC) Current  
AVEE Supply Voltage  
I (AVEE) Current  
DVCC Supply Voltage  
I (DVCC) Current  
ICC (Total) Supply Current  
Power Dissipation (Total)  
Power Supply Rejection Ratio (PSRR)  
Full  
Full  
Full  
Full  
Full  
Full  
Full  
Full  
Full  
VI  
V
VI  
V
VI  
V
I
+5.0  
336  
–5.0  
66  
+3.3  
20  
422  
2.1  
0.01  
V
mA  
V
mA  
V
mA  
mA  
W
1, 2, 3  
1, 2, 3  
7, 8  
520  
2.4  
0.02  
I
IV  
% FSR/% VS  
NOTES  
1Gain tests are performed on AIN1 over specified input voltage range.  
2Input capacitance specifications show only ceramic package capacitance.  
3Full power bandwidth is the frequency at which the spectral power of the fundamental frequency (as determined by FFT analysis) is reduced by 3 dB.  
4ENCODE driven by single-ended source; ENCODE bypassed to ground through 0.01 µF capacitor.  
5ENCODE may also be driven differentially in conjunction with ENCODE; see “Encoding the AD10265” for details.  
6Minimum and maximum conversion rates allow for variation in Encode Duty Cycle of 50% ± 5%.  
7Analog Input signal power at –1 dBFS; signal-to-noise ratio (SNR) is the ratio of signal level to total noise (first 5 harmonics removed). Encode = 65 MSPS.  
8Analog Input signal power at –1 dBFS; signal-to-noise and distortion (SINAD) is the ratio of signal level to total noise + harmonics. Encode = 65 MSPS.  
9Analog Input signal equal –1 dBFS; SFDR is ratio of converter full scale to worst spur.  
10Both input tones at –7 dBFS; two tone intermodulation distortion (IMD) rejection is the ratio of either tone to the worst 3rd order intermod product. f1 = 17.0 MHz  
± 100 kHz, f2 = 18.0 MHz ± 100 kHz.  
11Channel-to-channel isolation tested with A channel/50 ohm terminated <AIN2 grounded, and a full-scale signal applied to B channel (AIN1).  
All specifications guaranteed within 100 ms of initial power up regardless of sequencing.  
Specifications subject to change without notice.  
REV. 0  
–3–  
1234567...18

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