AD10242–Typical Performance Characteristics
80
–0.5
0
70
SNR (dB)
ENCODE = 40 MSPS
60
0.5
1
50
40
30
20
10
0
SFDR (dBFS)
1.5
2
ENCODE = 40 MSPS
2.5
3
A
= 1dBFs
IN
5
10
20
29.2
34.5
52.5
60.95
0
5
10
15
20
25
30
35
40
45
50
55
ANALOG INPUT FREQUENCY – MHz
INPUT FREQUENCY – MHz
Figure 18. SNR/Harm onics to AIN > Nyquist MSPS
Figure 19. Gain Flatness vs. Input Frequency
TH EO RY O F O P ERATIO N
AP P LYING TH E AD 10242
Encoding the AD 10242
T he AD10242 is designed to interface with T T L and CMOS
logic families. T he source used to drive the ENCODE pin(s)
must be clean and free from jitter. Sources with excessive jitter
will limit SNR and overall performance.
Refer to the block diagram. T he AD10242 employs three
monolithic ADI components per channel (AD9631, OP279, and
AD9042), along with multiple passive resistor networks and de-
coupling capacitors to fully integrate a complete 12-bit analog-
to-digital converter.
T he input signal is first passed through a precision laser
trimmed resistor divider allowing the user to externally select
operation with a full scale signal of ±0.5 V, ±1.0 V, or ±2.0 V by
choosing the proper input terminal for the application. The result
of the resistor divider is to apply a full-scale input of approxi-
mately 0.4 V to the noninverting input of the internal AD9631
amplifier.
AD10242
TTL OR CMOS
ENCODE
SOURCE
ENCODE
0.01µF
Figure 20. Single-Ended TTL/CMOS Encode
T he AD9631 provides the dc coupled level shift circuit required
for operation with the AD9042 ADC. Configuring the amplifier
in a noninverting mode the ac signal gain can be trimmed to
provide a constant input to the ADC centered around the inter-
nal reference voltage of the AD9042. T his allows the converter
to be used in multiple system applications without the need for
external gain and level shift circuitry normally requiring trim.
T he AD9631 was chosen for its superior ac performance and in-
put drive capabilities which have limited the ability of many am-
plifiers to drive high performance ADCs. As new amplifiers are
developed, pin compatible improvements are planned to incor-
porate the latest operational amplifier technology.
T he AD10242 encode inputs are connected to a differential in-
put stage (see Figure 4 under EQUIVALENT CIRCUIT S).
With no input connected to either the ENCODE or input, the
voltage divider bias the inputs to 1.6 volts. For T T L or CMOS
usage, the encode source should be connected to ENCODE
(Pins 29 and/or 51). ENCODE (Pins 28 and/or 52) should be
decoupled using a low inductance or microwave chip capacitor
to ground. Devices such as AVX 05085C103MA15, a
0.01 µF capacitor, work well.
P er for m ance Im pr ovem ents
It is possible to improve the performance of the AD10242
slightly by taking advantage of the internal characteristics of the
amplifier and converter combination. By increasing the +5 V
supply slightly, the user may be able to gain up to a 5 dB improve-
ment in SFDR over the entire frequency range of the converter.
It is not recommended to exceed +5.5 V on the analog supplies
as there are no performance benefits beyond that range and care
should be taken to avoid the absolute maximum ratings.
T he OP279 provides the buffer and inversion of the internal ref-
erence of the AD9042 in order to supply the summing node of
the AD9631 input amplifier. T his dc voltage is then summed
with the input voltage and applied to the input of the AD9042
ADC. T he reference voltage of the AD9042 is designed to track
internal offsets and drifts of the ADC and is used to ensure
matching over an extended temperature range of operation.
REV. A
–10–
5秒后页面跳转
深入解析CS8416引脚说明、参数、技术特点
TPA3116D2功放芯片参数详解、引脚说明
移位寄存器74HC165引脚说明、驱动程序示例解读
深入解析AD9833：DDS频率合成器的卓越性能与广泛应用
微信公众号
抖音公众号
浙公网安备 33010502006866号 浙ICP备10014259号-119
营业执照ICP证
数据手册
替代型号
如果您发现信息不准确，
