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ACS20K/SAMPLE

更新时间： 2024-01-23 15:24:05
品牌 Logo 应用领域
瑞萨 - RENESAS 输入元件逻辑集成电路
页数 文件大小 规格书
8页 87K
描述
AC SERIES, DUAL 4-INPUT NAND GATE, CDFP14, CERAMIC, DFP-14

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ACS20K/SAMPLE 技术参数

生命周期：Obsolete零件包装代码：DFP
包装说明：DFP,针数：14
Reach Compliance Code：unknownHTS代码：8542.39.00.01
风险等级：5.05系列：AC
JESD-30 代码：R-CDFP-F14逻辑集成电路类型：NAND GATE
功能数量：2输入次数：4
端子数量：14封装主体材料：CERAMIC, METAL-SEALED COFIRED
封装代码：DFP封装形状：RECTANGULAR
封装形式：FLATPACK传播延迟（tpd）：12 ns
认证状态：Not Qualified座面最大高度：2.92 mm
最大供电电压 (Vsup)：5.5 V最小供电电压 (Vsup)：4.5 V
标称供电电压 (Vsup)：5 V表面贴装：YES
技术：CMOS端子形式：FLAT
端子节距：1.27 mm端子位置：DUAL
宽度：6.285 mmBase Number Matches：1

ACS20K/SAMPLE 数据手册

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Specifications ACS20MS  
Intersil - Space Products MS Screening  
Wafer Lot Acceptance (All Lots) Method 5007 (Includes SEM) 100% Static Burn-In 2 Method 1015, 24 Hours at +125oC Min  
Radiation Verification (Each Wafer) Method 1019,  
4 Samples/Wafer, 0 Rejects  
100% Interim Electrical Test 2 (Note 1)  
100% Dynamic Burn-In Method 1015, 240 Hours at +125oC  
100% Nondestructive Bond Pull Method 2023  
100% Internal Visual Inspection Method 2010  
or 180 Hours at +135oC  
100% Interim Electrical Test 3 (Note 1)  
100% Final Electrical Test  
100% Temperature Cycling Method 1010 Condition C  
(-65o to +150oC)  
100% Fine and Gross Seal Method 1014  
100% Radiographics Method 2012 (2 Views)  
100% External Visual Method 2009  
100% Constant Acceleration  
100% PIND Testing  
100% External Visual Inspection  
100% Serialization  
Group A (All Tests) Method 5005 (Class S)  
Group B (Optional) Method 5005 (Class S) (Note 2)  
Group D (Optional) Method 5005 (Class S) (Note 2)  
CSI and/or GSI (Optional) (Note 2)  
100% Initial Electrical Test  
100% Static Burn-In 1 Method 1015, 24 Hours at +125oC Min  
100% Interim Electrical Test 1 (Note 1)  
Data Package Generation (Note 3)  
NOTES:  
1. Failures from interim electrical tests 1 and 2 are combined for determining PDA (PDA = 5% for subgroups 1, 7, 9 and delta failures com-  
bined, PDA = 3% for subgroup 7 failures). Interim electrical tests 3 PDA (PDA = 5% for subgroups 1, 7, 9 and delta failures combined,  
PDA = 3% for subgroup 7 failures).  
2. These steps are optional, and should be listed on the purchase order if required.  
3. Data Package Contents:  
Cover Sheet (P.O. Number, Customer Number, Lot Date Code, Intersil Number, Lot Number, Quantity).  
Certificate of Conformance (as found on shipper).  
Lot Serial Number Sheet (Good Unit(s) Serial Number and Lot Number).  
Variables Data (All Read, Record, and delta operations).  
Group A Attributes Data Summary.  
Wafer Lot Acceptance Report (Method 5007) to include reproductions of SEM photos. NOTE: SEM photos to include percent of step coverage.  
X-Ray Report and Film, including penetrometer measurements.  
GAMMA Radiation Report with initial shipment of devices from the same wafer lot; containing a Cover Page, Disposition, RAD Dose,  
Lot Number, Test Package, Spec Number(s), Test Equipment, etc. Irradiation Read and Record data will be on file at Intersil.  
Propagation Delay Timing Diagram and Load Circuit  
DUT  
TEST  
POINT  
VIH  
RL  
500Ω  
CL  
50pF  
INPUT  
VS  
VSS  
TPLH  
TPHL  
VOH  
VOL  
VS  
OUTPUT  
AC VOLTAGE LEVELS  
PARAMETER  
VCC  
ACS  
4.50  
4.50  
2.25  
0
UNITS  
V
V
V
V
V
VIH  
VS  
VIL  
GND  
0
Spec Number 518815  
5
12345678

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