5) Testing
configuration table. The Vdd
sense connections are provided
to allow the use of remote-
sensing power supplies for
compensation for PCB traces and
cable resistance.
ACPM-7812 Demoboard
Operation Instructions
- Signal Source
The CDMA modulated signal for
the test is generated using an
Agilent ESG-D4000A (or ESG-
D3000A) Digital Signal Generator
with the following settings:
1) Module Description
The ACPM-7812 is a fully matched
Power Amplifier. The sample
device is provided on a demon-
stration PC Board with SMA
connectors for RF inputs and
outputs, and a DC connector for
all bias and control I/O’s.
- Device Operation
CDMA Setup : Reverse
Spreading: On
Bits/Symbol: 1
1) Connect RF Input and Output
for the band under test.
2) Terminate all unused RF
ports into 50 Ohms.
3) Connect Vdd1 and Vdd2
supplies (including remote
sensing labeled Vdd1 S and
Vdd2 S on the board). Nomi-
nal voltage is 3.4V.
4) Apply RF input power accord-
ing to the values listed in
“Operation Data” in Data
Packet.
5) Connect Vref (Vcntl) supply
and set reference voltage to
the voltage shown in the data
packet. Note that the Vref
(Vcntl) pin is on the back side
of the demonstration board.
Please limit Vref (Vcntl) to not
exceed the corresponding
listed “DC Biasing Condition”
in the Data Packet. Note that
increasing Vref (Vcntl) over
the corresponding listed “DC
Biasing Condition” can result
in power decrease and
Data: PN15
Modulation: OQPSK
Chip Rate: 1.2288 Mcps
High Crest: On
Filter: Std
Phase Polarity: Invert
2) Circuit Operation
The design of the power module
(PAM) provide bias control via
Vref (Vcntl) to achieve optimal
RF performance and power
control. The control pin is
labeled Vref (Vcntl). Please refer
to Figure 3 for the block diagram
of this PAM.
- ACPR Measurement
The ACPR (and channel power) is
measured using an Agilent 4406
VSA with corresponding ACPR
offsets for IS-98c and JSTD-8.
Averaging of 10 is used for ACPR
measurements.
Typical Operation Conditions
(Vdd = 3.4V)
- DC Connection
Parameter
ACPM-7812
A DC connector is provided to
allow ease of connection to the
I/O’s. Wires can be soldered to
the connector pins, or the
connector can be removed and I/
O’s contacted via clip leads or
direct soldered connections. The
wiring of I/O’s are listed in
Figure 1 through 3 and Pin
Frequency Range
Output Power
Vcntl (Vref)
824 – 849 MHz
28.5 dBm
2.5 V
3) Maximum Ratings
Vdd
5.0V
current can exceed the rated
limit.
Drain Current
Vref (Vcntl)
RF input
1.5A
3V
10 dBm
-30 to 80°C
Power Module Block Diagram
Temperature
Vdd2
Vdd1
Please Note: Avoid Electrostatic Discharge
on all I/O’s.
On Chip
Inter-stage
Match
Passive
Output
Match
Power
Input
Match
4) Heat Sinking
Input
Output
The demonstration PC Board
provides an adequate heat sink.
Maximum device dissipation
should be kept below 2.5 Watts.
Vcntl (Vref)
19