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ACPL-P481 PDF预览

ACPL-P481

更新时间: 2024-10-03 01:19:03
品牌 Logo 应用领域
安华高科 - AVAGO 双极性晶体管
页数 文件大小 规格书
9页 230K
描述
Inverted Logic, High CMR Optocoupler for Intelligent Power Modules and IGBT/MOSFET Gate Drive

ACPL-P481 数据手册

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ACPL-P481 and ACPL-W481  
Inverted Logic, High CMR Optocoupler for Intelligent  
Power Modules and IGBT/MOSFET Gate Drive  
Data Sheet  
Description  
Features  
The high-speed ACPL-P481/W481 optocoupler contains Inverted output type (totem pole output)  
a GaAsP LED, photo detector and a Schmitt trigger that  
eliminates the need for external waveform conditioning  
circuits.  
Performance Specified for Common IPM Applications  
Over Industrial Temperature Range.  
Short Maximum Propagation Delays  
Minimized Pulse Width Distortion (PWD)  
Very High Common Mode Rejection (CMR)  
Hysteresis  
The totem pole output eliminates the need for a pull-up  
resistor. An Intelligent Power Module, Power MOSFET or  
IGBT can be driven directly.  
Propagation delay difference between devices has been  
minimized to maximize inverter efficiency through  
reduced switching dead time.  
Available in Stretched SO-6 Package.  
Package Clearance/Creepage at 8 mm (ACPL-W481)  
Safety Approval: (pending)  
Applications  
– UL Recognized with 3750 V  
(5000 Vrms for  
rms  
ACPL-W481) for 1 minute per UL1577.  
– CSA Approved.  
– IEC/EN/DIN EN 60747-5-5 Approved with V  
IPM Interface Isolation  
Isolated IGBT/MOSFET Gate Drive  
AC and Brushless DC Motor Drives  
Industrial Inverters  
=
for  
IORM  
891 V  
for ACPL-P481 and V  
= 1140 V  
peak  
IORM  
peak  
ACPL-W481, under option 060.  
General Digital Isolation  
Specifications  
Functional Diagram  
Wide Operating Temperature Range: –40°C to 100°C.  
Maximum Propagation Delay t / t = 350 ns  
PHL PLH  
Anode 1  
N.C. 2  
6 VCC  
Maximum Pulse Width Distortion (PWD) = 250 ns.  
Propagation Delay Difference: Min. –100 ns, Max. 250 ns  
5 VO  
Wide Operating V Range: 4.5 V to 20 V  
CC  
Cathode 3  
4 Ground  
SHIELD  
20 kV/µs Minimum Common Mode Rejection (CMR) at  
Note: A 0.1 µF bypass capacitor must be connected between pins 4 and 6.  
V
CM  
= 1000 V.  
Truth Table (Positive Logic)  
LED  
ON  
V
O
LOW  
OFF  
HIGH  
CAUTION: It is advised that normal static precautions be taken in handling and assembly  
of this component to prevent damage and/or degradation which may be induced by ESD.  

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