5秒后页面跳转
捷配首页

Datasheet > ACE9030M/IW/FP1N
ACE9030M/IW/FP1N PDF预览

ACE9030M/IW/FP1N

更新时间： 2024-02-25 15:39:59
品牌 Logo 应用领域
MITEL 电信集成电路无线
页数 文件大小 规格书
39页 382K
描述
Radio Interface and Twin Synthesiser

阅读下载

获取价格

ACE9030M/IW/FP1N 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
包装说明：LFQFP, QFP64,.47SQ,20Reach Compliance Code：compliant
HTS代码：8542.39.00.01风险等级：5.17
Is Samacsys：NJESD-30 代码：S-PQFP-G64
JESD-609代码：e0长度：10 mm
湿度敏感等级：3功能数量：1
端子数量：64最高工作温度：85 °C
最低工作温度：-40 °C封装主体材料：PLASTIC/EPOXY
封装代码：LFQFP封装等效代码：QFP64,.47SQ,20
封装形状：SQUARE封装形式：FLATPACK, LOW PROFILE, FINE PITCH
峰值回流温度（摄氏度）：240电源：3.6/5 V
认证状态：Not Qualified座面最大高度：1.6 mm
子类别：Other Telecom ICs最大压摆率：0.007 mA
标称供电电压：3.75 V表面贴装：YES
电信集成电路类型：TELECOM CIRCUIT温度等级：INDUSTRIAL
端子面层：Tin/Lead (Sn/Pb)端子形式：GULL WING
端子节距：0.5 mm端子位置：QUAD
处于峰值回流温度下的最长时间：30宽度：10 mm
Base Number Matches：1

ACE9030M/IW/FP1N 数据手册

 浏览型号ACE9030M/IW/FP1N的Datasheet PDF文件第3页浏览型号ACE9030M/IW/FP1N的Datasheet PDF文件第4页浏览型号ACE9030M/IW/FP1N的Datasheet PDF文件第5页浏览型号ACE9030M/IW/FP1N的Datasheet PDF文件第7页浏览型号ACE9030M/IW/FP1N的Datasheet PDF文件第8页浏览型号ACE9030M/IW/FP1N的Datasheet PDF文件第9页 
ACE9030  
ELECTRICAL CHARACTERISTICS  
These characteristics apply over these ranges of conditions (unless otherwise stated):  
TAMB = – 40 °C to + 85 °C, VDD = + 3·6 to + 5·0 V, GND ref. = VSS  
D.C. Characteristics (continued)  
Parameter  
Min.  
Typ.  
Max.  
Unit Conditions  
Synthesiser charge pump current  
Current setting resistor RSMA  
Current setting resistor RSC  
19  
19  
39  
39  
78  
78  
kΩ Note 3  
kΩ Note 3  
External capacitance on pin RSMA  
External capacitance on pin RSC  
Bias current IRSMA (nominally 1·25V / RSMA  
Bias current IRSC (nominally 1·25V / RSC)  
Iprop(0) scaling accuracy, pin PDP  
Iprop(1) scaling accuracy, pin PDP  
Iint scaling accuracy, pin PDI  
Icomp(0) scaling accuracy, pin PDP  
5
5
pF Ensures stable  
pF bias current.  
µA RSMA = 39 kΩ  
µA RSC = 39 kΩ  
)
28·8  
28·8  
–10  
–10  
–10  
–10  
32  
32  
35·2  
35·2  
+10  
+10  
+10  
+10  
%
%
%
%
@ 200 µA. Note 4  
@ 800 µA. Note 4  
@ 4 mA. Note 4  
@ ACC x 0·2 µA  
Note 4  
Icomp(1) scaling accuracy, pin PDP  
Icomp(2) scaling accuracy, pin PDI  
–10  
–10  
+10  
+10  
%
%
@ ACC x 0·8 µA  
Note 4  
@ ACC x 4 µA  
Note 4  
Iauxil scaling accuracy, pin PDA  
Auxiliary Charge Pump,  
–5  
–10  
+5  
+10  
%
%
@ 256 µA. Note 4  
Note 5  
Up or Down IAUX current variation  
Main Charge Pumps,  
–10  
+10  
%
Note 6  
Up or Down IMAIN or IINTEGRAL current variation  
Iprop(0) or Iprop(1) setting from PDP pin  
Iint setting from PDI pin  
Icomp(0) or Icomp(1) setting from PDP pin  
Icomp(2) setting from PDI pin  
1·0  
5
12  
180  
512  
mA  
mA  
µA  
µA  
µA  
Iauxil setting from PDA pin  
Notes  
3. The circuit is defined with resistors RSMA and RSC connected from pins RSMA and RSC to VSSSA but in most practical applications all VSS pins  
will be connected to a ground plane so RSMA and RSC should then also be connected to this ground plane.  
4. The charge pump currents are specified to this accuracy when the relevant output pin is at a potential of VDD/2 and with RSMA = 39 kΩ, CN  
= 200, L= 1, K = 5, RSC = 19 kΩ. The nominal value is set by external resistors and by programming registers, as defined in Table 6. Tolerances  
in the internal Bandgap voltage and bias circuits are within the limits given for IRSMA and IRSC, the scaling accuracy of the multiplying DAC’s  
is within these limits given for Iprop(0), Iprop(1), Iint, Icomp(0), Icomp(1), Icomp(2), and auxil.  
5. The Auxiliary charge pump output voltage is referred to as VPDA and the output current IAUX is the Up or Down current measured when  
VPDA = VDD/2.  
The conditions for the variation limits for the Up current are:  
either  
or  
IAUX = 128 or 256 µA  
IAUX = 512 µA  
and  
and  
0 < VPDA < VDD – 0·5 V  
0 < VPDA < VDD – 0·65 V  
The conditions for the variation limits for the Down current are:  
either  
or  
IAUX = 128 or 256 µA  
IAUX = 512 µA  
and  
and  
0·5 V < VPDA < VDD  
0·65 V < VPDA < VDD  
6. The Main charge pump output voltage at pin PDP is referred to as VPDP and at pin PDI as VPDI. The output currents IMAIN and IINTEGRAL are the  
up or down current Iprop(0), Iprop(1) or Iint measured when VPDP or VDPI = VDD/2.  
The conditions for the variation limits for the Up current are :  
IMAIN = 100 to 1000 µA or IINTEGRAL = 1 to 5 mA and 0 < VPDP < VDD – 0·45 V  
The conditions for the variation limits for the Down current are:  
IMAIN = 100 to 1000 µA or IINTEGRAL = 1 to 5 mA and 0·45 V < VPDP < VDD  
6
1...3456789...39

下载PDF

与ACE9030M/IW/FP1N相关器件

型号 品牌 描述 获取价格 数据表
ACE9030M/IW/FP1Q MITEL Radio Interface and Twin Synthesiser

获取价格
ACE9030M/IW/FP2N MITEL Radio Interface and Twin Synthesiser

获取价格
ACE9030M/IW/FP2Q MITEL Radio Interface and Twin Synthesiser

获取价格
ACE9030M/IW/FP3Q MICROSEMI SPECIALTY TELECOM CIRCUIT, PQFP64, 10 X 10 MM, 0.50 MM PITCH, LEAD FREE, TQFP-64

获取价格
ACE9030MIWFP1N MITEL Radio Interface and Twin Synthesiser

获取价格
ACE9030MIWFP1Q MITEL Radio Interface and Twin Synthesiser

获取价格

与ACE9030M/IW/FP1N相关文章

您还可以找


热门产品
PCB打样/小批量
铝基板
BOM智能配单
PCBA制造
钣金
精密CNC
模具注塑
薄膜开关
精选活动
PCBA打样特惠
四六层板品质升级
铝基板品质升级
一体化电子制造
DFM下载
服务支持
企业认证
产品展示
工厂展示
工艺能力
积分商城
关于捷配
捷配简介
企业文化
公司动态
人才招聘
联系我们
帮助中心
下单流程
付款流程
开票流程
常见问题
全球PCB制造服务专线 400-613-0088

工作时间：9:00-21:00

CEO邮箱：ceo@jiepei.com

投诉邮箱：tousu@jiepei.com

捷配网-微信公众号 微信公众号
捷配网-微信公众号 抖音公众号
资质认证：
合作快递：
支付方式：
Copyright © 2024 Jiepei.com Inc. All Rights Reserved. 版权所有:杭州捷配信息科技有限公司 浙公网安备 33010502006866号 浙ICP备10014259号-119 营业执照ICP证