Revision History
Document Revision
Description
Date
Number
Number
320122
001
• Initial Release
• Chapter 1
July 2008
— Added Section 1.3: GS45 Feature Support
— Added Section 1.4: GL40 Feature Support
• Chapter 10
— Added GS45 and GL40 power characteristic data to Table 24
— Added GS45 and GL40 current data to Table 24
— Added GS45 current data to Table 27
320122
002
August 2008
• Section 13.3: Added clocking information for GS45 and GL40
• Section 16.4 and Section 16.5: Added Ballout and Signal Names
for GS45
• Section 19.1.36: Added Configuration Register Description for
GS45 and GL40
• Chapter 1
— Section 1.3: Added GM47 Feature Support
— Section 1.3.3: Updated GS45 Graphics Core Render Clock
— Section 1.4.3: Updated GL40 Graphics Core Render Clock
• Chapter 5
— Section 5.1:Added GS45 memory-down support on two
channels
• Chapter 10
— Section 10.1: Added GM47, updated GS45 and GL40 TDP
numbers in Table 23
— Section 10.1: Added GM47, GS45 IVCC and updated GL40
IVCC_AXG specification in Table 24
— Section 10.1: Added GM47 and GL40 IVCC_AXF specification
in Table 27
• Chapter 13
— Section 13.3: Added GM47 GMCH Clock Frequency Support
— Section 13.3: Added GL40 conversion stepping updates to
320122
003
December 2008
Clock Frequency Support
• Chapter 16
— Section 16.3: Updated Intel 4 Series Express Chipset
package drawing in Figure 25
• Chapter 19
— Section 19.1.36: Added GM47 GFX Software and DDR2
Capability and updated DDR3 and FSB Capability in CAPID
Register
• Chapter 20
— Section 20.4.4: Updated RST_EVNT definition in SLFRCS
Register
• Chapter 21
— Section 21.1.5: Added conversion A-1 stepping revision ID
in RID Register
• Chapter 23
— Section 23.1.1: Corrected Intel ME Identifier Register
default value
10
Datasheet