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ABX2088OC PDF预览

ABX2088OC

更新时间: 2024-01-07 04:20:28
品牌 Logo 应用领域
ABRACON 石英晶振
页数 文件大小 规格书
6页 67K
描述
Low Phase Noise XO (9.5-65MHz Output)

ABX2088OC 技术参数

生命周期:Active零件包装代码:TSSOP
包装说明:TSSOP,针数:16
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.79
其他特性:IT ALSO OPERATES AT 2.5V NOM SUPPLYJESD-30 代码:R-PDSO-G16
长度:5 mm端子数量:16
最高工作温度:85 °C最低工作温度:-40 °C
最大输出时钟频率:65 MHz封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH主时钟/晶体标称频率:65 MHz
认证状态:Not Qualified座面最大高度:1.2 mm
最大供电电压:3.63 V最小供电电压:2.97 V
标称供电电压:3.3 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子形式:GULL WING端子节距:0.65 mm
端子位置:DUAL宽度:4.4 mm
uPs/uCs/外围集成电路类型:CLOCK GENERATOR, OTHERBase Number Matches:1

ABX2088OC 数据手册

 浏览型号ABX2088OC的Datasheet PDF文件第2页浏览型号ABX2088OC的Datasheet PDF文件第3页浏览型号ABX2088OC的Datasheet PDF文件第4页浏览型号ABX2088OC的Datasheet PDF文件第5页浏览型号ABX2088OC的Datasheet PDF文件第6页 
ABX2088/89  
Low Phase Noise XO (9.5-65MHz Output)  
FEATURES  
PIN CONFIGURATION  
19MHz to 65MHz crystal input.  
Output range: 9.5MHz – 65MHz  
Complementary outputs: PECL or LVDS output.  
Selectable OE Logic (enable high or enable low).  
Supports 2.5V or 3.3V Power Supply.  
Available in 16 pin TSSOP package.  
VDD  
XIN  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
10  
DNC  
DNC  
XOUT  
DNC  
S2  
GNDBUF  
QBAR  
VDDBUF  
Q
OE  
DESCRIPTION  
N/C  
GNDBUF  
GND  
The ABX2088 (PECL) and ABX2089 (LVDS) are XO  
ICs specifically designed to work with fundamental  
or 3rd OT crystals between 19MHz and 65MHz. The  
selectable divide by two feature extends the  
operation range from 9.5MHz to 65MHz. They  
require very low current into the crystal resulting in  
better overall stability. The OE logic feature allows  
selection of enable high or enable low.  
GND  
9
OUTPUT SELECTION AND ENABLE  
OE_SELECT  
OE_CTRL  
State  
0
Tri-state  
0
1 (Default) Output enabled  
0 (Default) Output enabled  
BLOCK DIAGRAM  
1 (Default)  
1
Tri-state  
Input selection: Bond to GND to set to “0”, bond to VDD to set to “1”  
No connection results to “default” setting through  
internal pull-up/-down.  
O
Q
OE_CTRL:  
Logical states defined by PECL levels if  
OE_SELECT is “1”  
Logical states defined by CMOS levels if  
OE_SELECT is “0”  
Q
Oscillator  
Amplifier  
X+  
S2  
X-  
OUTPUT FREQUENCY DIVIDE BY  
TWO SELECTOR  
ABX208X Block Diagram  
S2  
Output  
0
1
Intput/2  
Input  
30332 Esperanza., Rancho Santa Margarita, Ca 92688 Ph: 949-546-8000 Fax: 949-546-8001 www.Abracon.com 03/21/05 Page 1  

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