PRODUCT DATASHEET
AAT4684
OVPSwitchTM
Over-Voltage Protection Switch
Over-Voltage Protection
Application Information
The AAT4684 adjustable version has a 1.1V ±1.5% over-
voltage trip threshold on the OVP pin. With a resistor
divider on OVP pin from IN to GND, the over-voltage trip
point can be adjusted anywhere within the input voltage
range (see Table 1). Once the over-voltage trip level is
triggered, the PMOS switch controller will shut off the
PMOS in less than 1μs.
Over-Voltage Protection
The AAT4684 over-voltage protection circuit provides
fast protection against transient voltage spikes and short
duration spikes of high voltage from the power supply
lines. AAT4684 can quickly disconnect the input supply
from the load and not cause any damage to sensitive
components
The AAT4684 fixed version is also available where the
resistor divider is internally integrated with the input
voltage trip point at 6.5V. The fixed version of AAT4684
does not have a connection to the internal OVP circuitry
and the pin #11 is designed to be not connected.
In portable product applications, if the user removes the
battery pack during charging, this action can create
large transients and a high voltage spike can occur
which can damage other electronic devices in the prod-
uct such as the battery charger. A hot plug of the AC/DC
wall adapter into the AC outlet can create and release a
voltage spike from the transformer. As a result, some
sensitive devices within the product can be damaged.
With the AAT4684 placed between the power lines and
the sensitive devices, the voltage spike can be kept
away and the input supply disconnected from other
devices in 0.7μs.
FLT Output
The FLT output is an active-low open-drain fault (OV)
reporting output. A pull-up resistor should be connected
from FLT to the logic I/O voltage of the host system. FLT
will be asserted immediately if an over-voltage fault
occurs (only about a 1μs inherited internal circuit delay).
A 10ms blanking is applied to FLT signal prior to de-
assertion.
Figure 2 shows the response time of over-voltage pro-
tection from the test circuit (Figure 1). The input volt-
age is rapidly increased from 5V to 12V by a voltage
surge or voltage spike. The voltage at the OVP pin is also
increased until the trip point is triggered. At this point,
the FLT pin is pulled low and the output voltage starts to
fall. Figure 3 shows a zoom-in scope capture of the OVP
response time; the output is disconnected from the input
in as little as 700ns.
EN Input
EN is an active-low enable input. EN is driven low, con-
nected to ground, or left floating for normal device
operation. Taking the EN high turns off the MOSFET. In
the case of an over-voltage or UVLO condition toggling
the EN will not override the fault condition and the
switch will remain off.
Adjustable Version - Over-Voltage
Protection Resistors
Device Operation
On initial power-up, if VIN < UVLO or if VOVP > VOVP_TH
The over-voltage protection threshold is programmed
with two resistors, R1 and R2. To limit the current going
through the external resistor string while maintaining
good noise immunity, use smaller resistor values, such
as 10KΩ for R2. Using a larger value will further reduce
the system current, but will also increase the impedance
of the OVP node, making it more sensitive to external
noise and interference. A suggested value for R2 is
110KΩ. Table 1 summarizes resistor values for various
over-voltage settings. Use 1% tolerance metal film
resistors for programming the desired OVP setting.
(1.1V), the PMOS is held off. If UVLO < VIN, VOVP
OVP_TH, and EN is low, the device enters startup after a
10ms internal delay.
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