Datasheet > AAT3244

AAT3244

更新时间： 2022-04-23 23:00:11

品牌	Logo	应用领域
ANALOGICTECH		稳压器
页数	文件大小	规格书
15页	807K
描述
300mA Adjustable Dual CMOS Low Voltage LDO Linear Regulator

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中文翻译

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AAT3244 数据手册

AAT3244

300mA Adjustable Dual CMOS

Low Voltage LDO Linear Regulator

For a 300mA output current and a 2.7V drop across

the AAT3244 at an ambient temperature of 25°C,

the maximum on-time duty cycle for the device

would be 46.3ꢀ.

4. The resistance of the trace from the load returns

to GND (Pin 10) should be kept to a minimum.

This will help to minimize any error in DC regu-

lation due to differences in the potential of the

internal signal ground and the power ground.

5. The feedback node is connected directly to the

non-inverting input of the error amplifier, thus

any noise or ripple from the divider resistors

will be subsequently amplified by the gain of

the error amplifier. This effect can increase

noise seen on the LDO regulator output, as

well as reduce the maximum possible power

supply ripple rejection. For low output noise

and highest possible power supply ripple rejec-

tion performance, it is critical to connect the

divider resistors (R2 and R4) and output

capacitors (C4 and C5) directly to the LDO reg-

ulator ground pin. This method will eliminate

any load noise or ripple current feedback

through the LDO regulator.

Under-Voltage Lockout

Under-voltage lockout (UVLO) guarantees suffi-

cient V_CCbias and proper operation of all internal

circuits prior to activation.

Printed Circuit Board Layout

Recommendations

The suggested PCB layout for the AAT3244 in a

TSOPJW-12 package is shown in Figures 2 and 3.

The following guidelines should be used to help

ensure a proper layout.

1. The input capacitors (C1and C2) should con-

nect as closely as possible to input pins (Pin 2

and Pin 5) and GND (Pin 10).

2. The output traces of the feedback resistors (R1

and R3) should be separate from any power

trace and connect as closely as possible to the

load point. Sensing along a high-current load

trace will degrade DC load regulation. Feedback

resistors should be placed as closely as possible

to the FB pin (Pin 3 and Pin 4) to minimize the

length of the high impedance feedback trace.

Evaluation Board Layout

The AAT3244 evaluation layout follows the recom-

mend printed circuit board layout procedures and

can be used as an example for good application

layouts (See Figures 2 and 3).

Note: Board layout shown is not to scale.

Figure 2: AAT3244 Evaluation Board

Top Side Layout.

Figure 3: AAT3244 Evaluation Board

Bottom Side Layout.

3244.2007.08.1.1

1...10 11 121314 15

中文翻译

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AAT3244ITP-AA-T1	ANALOGICTECH	300mA Adjustable Dual CMOS Low Voltage LDO Linear Regulator	获取价格
AAT3258	AAT	300mA LDO Linear Regulator with uP Reset	获取价格
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AAT3258ITS-2.8-Y-T1	ANALOGICTECH	300mA LDO Linear Regulator with UP Reset	获取价格
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