AAT3201
150mA OmniPower™ LDO Linear Regulator
PD(MAX)
= (VIN - VOUT)IOUT + (VIN x IGND)
High Peak Output Current Applications
PD(150mA) = (5.0V - 2.5V)150mA + (5.0V x 20µA)
PD(150mA) = 375mW
Some applications require the LDO regulator to
operate at continuous nominal levels with short
duration, high-current peaks. The duty cycles for
both output current levels must be taken into
account. To do so, first calculate the power dissi-
pation at the nominal continuous level, then factor
in the addition power dissipation due to the short
duration, high-current peaks.
PD(8.2%D/C) = %DC x PD(150mA)
PD(8.2%D/C) = 0.082 x 375mW
PD(8.2%D/C) = 30.75mW
The power dissipation for a 150mA load occurring
for 8.2% of the duty cycle will be 20.9mW. Finally,
the two power dissipation levels can summed to
determine the total true power dissipation under the
varied load.
For example, a 2.5V system using an AAT3201IGV-
2.5-T1 operates at a continuous 100mA load current
level and has short 150mA current peaks. The cur-
rent peak occurs for 378µs out of a 4.61ms period.
It will be assumed the input voltage is 5.0V.
PD(total) = PD(100mA) + PD(150mA)
PD(total) = 229.5mW + 30.75mW
P
D(total) = 260.25mW
First, the current duty-cycle percentage must be
calculated:
The maximum power dissipation for the AAT3201
operating at an ambient temperature of 85°C is
267mW. The device in this example will have a total
power dissipation of 260.25mW. This is within the
thermal limits for safe operation of the device.
% Peak Duty Cycle: X/100 = 378ms/4.61ms
% Peak Duty Cycle = 8.2%
The LDO regulator will be under the 100mA load
for 91.8% of the 4.61ms period and have 150mA
peaks occurring for 8.2% of the time. Next, the
continuous nominal power dissipation for the
100mA load should be determined then multiplied
by the duty cycle to conclude the actual power dis-
sipation over time.
Printed Circuit Board Layout
Recommendations
In order to obtain the maximum performance from
the AAT3201 LDO regulator, careful consideration
should be given to the printed circuit board layout. If
grounding connections are not properly made,
power supply ripple rejection and LDO regulator
transient response can be compromised.
PD(MAX)
= (VIN - VOUT)IOUT + (VIN x IGND)
PD(100mA) = (5.0V - 2.5V)100mA + (5.0V x 20µA)
PD(100mA) = 250mW
The LDO regulator external capacitors CIN and
COUT should be connected as directly as possible
to the ground pin of the LDO regulator. For maxi-
mum performance with the AAT3201, the ground
pin connection should then be made directly back
to the ground or common of the source power sup-
ply. If a direct ground return path is not possible
due to printed circuit board layout limitations, the
LDO ground pin should then be connected to the
common ground plane in the application layout.
PD(91.8%D/C) = %DC x PD(100mA)
PD(91.8%D/C) = 0.918 x 250mW
PD(91.8%D/C) = 229.5mW
The power dissipation for a 100mA load occurring
for 91.8% of the duty cycle will be 229.5mW. Now
the power dissipation for the remaining 8.2% of the
duty cycle at the 150mA load can be calculated:
3201.2006.01.1.2
13
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