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AAT2847IML-QI-T1

更新时间： 2024-02-08 20:46:54

品牌	Logo	应用领域
ANALOGICTECH		驱动器驱动程序和接口接口集成电路
页数	文件大小	规格书
20页	382K
描述
Four-Channel Backlight Driver with Dual LDOs

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技术参数
数据手册

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AAT2847IML-QI-T1 技术参数

生命周期：	Active	包装说明：	,
Reach Compliance Code：	unknown	ECCN代码：	EAR99
HTS代码：	8542.39.00.01	风险等级：	5.69
接口集成电路类型：	LED DISPLAY DRIVER	Base Number Matches：	1

AAT2847IML-QI-T1 数据手册

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AAT2847

Four-Channel Backlight Driver with Dual LDOs

LDOs require a 2.2µF or greater output capacitor.

Figures 5 and 6 illustrate an example PCB layout.

The bottom of the package features an exposed

metal pad. The exposed pad acts, thermally, to

transfer heat from the chip and, electrically, as a

ground connection.

The required input capacitor (C_IN) is 2.2µF or

greater.

Ceramic capacitors offer many advantages over

their tantalum and aluminum electrolytic counter-

parts. A ceramic capacitor typically has very low

ESR, is lowest cost, has a smaller printed circuit

board (PCB) footprint, and is non-polarized. Low

ESR ceramic capacitors maximize charge pump

transient response.

The junction-to-ambient thermal resistance (θ_JA) for

the connection can be significantly reduced by fol-

lowing a couple of important PCB design guidelines.

The PCB area directly underneath the package

should be plated so that the exposed paddle can be

mated to the top layer PCB copper during the reflow

process. Multiple copper plated thru-holes should

be used to electrically and thermally connect the top

surface pad area to additional ground plane(s).

Before choosing a particular capacitor, verify the

capacitor’s performance with the characteristics

illustrated in the component’s data sheet.

Performance verification will help avoid undesirable

component related performance deficiencies.

The chip ground is internally connected to both the

exposed pad and to the AGND and PGND pins. It is

good practice to connect the GND pins to the

exposed pad area with traces as shown in Figure 4.

PCB Layout

To achieve adequate electrical and thermal per-

formance, careful attention must be given to the

PCB layout. In the worst-case operating condition,

the chip must dissipate considerable power at full

load. Adequate heat-sinking must be achieved to

ensure intended operation.

The flying capacitors (C1 and C2), input capacitor

(C4), and output capacitors (C3, C5, and C6) should

be connected as close as possible to the IC. In addi-

tion to the external passive components being placed

as close as possible to the IC, all traces connecting

the AAT2847 should be as short and wide as possible

to minimize path resistance and potential coupling.

Figure 4: AAT2847 Package Layout.

2847.2007.09.1.0

1...13 14 151617 18 19 20

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