PRODUCT DATASHEET
AAT1157
TM
SwitchReg
1MHz 1.2A Buck DC/DC Converter
the IC. This keeps the high frequency content of the
input current localized, minimizing radiated and con-
ducted EMI while facilitating optimum performance of
the AAT1157. Ceramic X5R or X7R capacitors are ideal
for this function. The size required will vary depending
on the load, output voltage, and input voltage source
impedance characteristics. Values range from 1μF to
10μF. The input capacitor RMS current varies with the
input voltage and the output voltage. The equation for
the RMS current in the input capacitor is:
For an X7R or X5R ceramic capacitor, the ESR is very low
and the dissipation due to the RMS current of the capac-
itor is not a concern. Tantalum capacitors with suffi-
ciently low ESR to meet output voltage ripple require-
ments also have an RMS current rating well beyond that
actually seen in this application.
Layout
The suggested PCB layout for the AAT1157 is shown in
Figures 2 and 3. The following guidelines should be used
to help insure a proper layout.
VO
VIN
⎛
VO ⎞
VIN ⎠
IRMS = IO ⋅
⋅ 1 -
⎝
1. The input capacitor (C1) should connect as closely as
possible to VP (Pins 10, 11, and 12) and PGND (Pins
1, 2, and 3).
2. C3-C4 and L1 should be connected as closely as pos-
sible. The connection from L1 to the LX node should
be as short as possible.
The input capacitor RMS ripple current reaches a maxi-
mum when VIN is two times the output voltage where it
is approximately one half of the load current. Losses
associated with the input ceramic capacitor are typically
minimal and are not an issue. The proper placement of
the input capacitor can be seen in the evaluation board
layout (C1 in Figure 2).
3. The trace connecting the FB pin to resistors R3 and
R4 should be as short as possible by placing R3 and
R4 immediately next to the AAT1157. The sense
trace connection R3 to the output voltage should be
separate from any power trace and connect as close-
ly as possible to the load point. Sensing along a high-
current load trace will degrade DC load regulation.
4. The resistance of the trace from the load return to
the PGND (Pins 1, 2, and 3) and SGND (Pin 5) should
be kept to a minimum. This will help to minimize any
error in DC regulation due to differences in the
potential of the internal signal ground and the power
ground. SGND (Pin 5) can also be used to remotely
sense the output ground at the point of load to
improve regulation.
5. A low pass filter (R1 and C2) provides a cleaner bias
source for the AAT1157 active circuitry. C2 should be
placed as closely as possible to SGND (Pin 5) and VCC
(Pin 9).
6. For good heat transfer, four 15 mil vias spaced on a
26 mil grid connect the QFN central paddle to the bot-
tom side ground plane, as shown in Figures 2 and 3.
Output Capacitor
Since there are no external compensation components,
the output capacitor has a strong effect on loop stability.
Larger output capacitance reduces the crossover fre-
quency while increasing the phase margin. For the 2.5V
1.2A design using the 3.0μH inductor, a 40μF capacitor
provides a stable output. Table 1 provides a list of sug-
gested output capacitor values for various output volt-
ages. In addition to assisting in stability, the output
capacitor limits the output ripple and provides holdup
during large load transitions. The output capacitor RMS
ripple current is given by:
VOUT
⋅
(VIN - VOUT
VIN
)
1
IRMS
=
⋅
L
⋅ F ⋅
2
⋅ 3
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