A8519 and
A8519-1
Wide Input Voltage Range, High-Efficiency,
Fault-Tolerant LED Driver
PINOUT DIAGRAMS
20-Pin TSSOP with Exposed Thermal Pad (suffix LP)
28-Pin QFN with Exposed Thermal Pad (suffix ET)
1
2
20 LED4
19 LED3
18 LED2
17 LED1
16 AGND
15 ISET
14 FSET
13 PWM
12 APWM
11 VDD
COMP
PGND
OVP
3
VIN
1
2
3
4
5
6
7
21 PGND
20 PGND
19 PGND
18 COMP
17 NC
4
VOUT
SW
NC
FAULT
CLKOUT
VDD
5
PAD
6
GATE
VSENSE
VIN
7
8
APWM
PWM
16 LED4
15 LED3
9
FAULT
CLKOUT
10
Terminal List Table
Pin Number
Name
Function
LP
ET
Output of the error amplifier and compensation node. Connect an Rz-Cz-Cp network from this pin to GND
for control loop compensation.
1
18
COMP
PGND
OVP
2
3
19,20,21
22
Power ground for internal N-channel MOSFET switching device. Connect to PCB ground plane.
Overvoltage protection. Connect external resistor from VOUT to this pin to adjust the overvoltage protection
level.
4
5
6
23
25,26
27
VOUT
SW
Connect directly to boost output voltage.
The drain of the internal N-channel MOSFET switching device of the boost converter.
Output gate driver pin for external P-channel MOSFET control.
GATE
Connect this pin to the negative sense side of the current sense resistor Rsc. The threshold voltage is
measured as VIN-VSENSE. There is also fixed current sink to allow for trip threshold adjustment.
7
8
9
28
1
VSENSE
VIN
Input power to the IC as well as the positive input used for current sense resistor.
The pin is an open-drain type configuration that will be pulled low when a fault occurs. Connect a 100 kW
resistor between this pin and desired logic level voltage.
3
FAULT
Logic output representing the switching frequency of internal boost oscillator. This allows other converters to
be synchronized to the same frequency (with the same frequency dithering, if applicable)
10
11
12
4
5
6
CLKOUT
VDD
Output of internal LDO (bias regulator). Connect a 1 μF decoupling capacitor between this pin and GND.
Analog trimming option or dimming. Applying a digital PWM signal to this pin adjusts the internal IISET
current.
APWM
Enables the IC when this pin is pulled high. Also serves to control the LED intensity by using pulse-width
modulation. Typical PWM dimming frequency is in the range of 100 to 400 Hz.
13
14
7
8
PWM
FSET
Frequency/synchronization pin. A resistor RFSET from this pin to GND sets the switching frequency (with
dithering superimposed). It can also be used to synchronize two or more converters in the system to an
external frequency between 260 kHz and 2.3 MHz (dithering is disabled in this case).
15
16
9
ISET
Connect RISET resistor between this pin and GND to set the desired LED current setting.
LED current ground. Connect to PCB ground plane.
10,11
AGND
17,18,
19,20
13,14,
15,16
LED current sinks #1 to 4. Connect the cathode of each LED string to associated pin. Unused LED pin must
be terminated to GND through a 3.09 kΩ resistor.
LED 1-4
NC
2,12,
17,24
–
–
No connect. Leave open or connect to GND.
Exposed pad of the package providing enhanced thermal dissipation. This pad must be connected to the
ground plane(s) of the PCB with at least 8 vias, directly in the pad.
–
PAD
Allegro MicroSystems, LLC
115 Northeast Cutoff
5
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
5秒后页面跳转
PCF8574资料解读：主要参数分析、引脚说明
AD637数据手册解读：主要特性、引脚及其功能解读、电气参数
ADUM1201资料手册解读：参数分析、引脚说明、应用分析
一文带你了解压敏电阻器在直流电路中的过压保护作用
微信公众号
抖音公众号
浙公网安备 33010502006866号 浙ICP备10014259号-119
营业执照ICP证
数据手册
如果您发现信息不准确，
