5秒后页面跳转
捷配首页

Datasheet > 信号电路 > 汽车电路> A8450KLB-T
A8450KLB-T PDF预览

A8450KLB-T

更新时间： 2024-02-21 13:22:50
品牌 Logo 应用领域
急速微 - ALLEGRO 稳压器
页数 文件大小 规格书
15页 547K
描述
Automotive Analog Circuit, PDSO24

阅读下载

中文翻译

获取价格

A8450KLB-T 技术参数

生命周期：ObsoleteReach Compliance Code：unknown
风险等级：5.84特性阻抗：50 Ω
最大输入功率 (CW)：43.98 dBm最大工作频率：4000 MHz
最小工作频率：最高工作温度：125 °C
最低工作温度：-55 °C射频/微波设备类型：FIXED ATTENUATOR
最大电压驻波比：1.35Base Number Matches：1

A8450KLB-T 数据手册

 浏览型号A8450KLB-T的Datasheet PDF文件第6页浏览型号A8450KLB-T的Datasheet PDF文件第7页浏览型号A8450KLB-T的Datasheet PDF文件第8页浏览型号A8450KLB-T的Datasheet PDF文件第10页浏览型号A8450KLB-T的Datasheet PDF文件第11页浏览型号A8450KLB-T的Datasheet PDF文件第12页 
A8450  
Automotive Multioutput Voltage Regulator  
ENBAT is an edge-triggered enable (logic 1 ≥ 2.7 V), which  
on either regulator, VOC , is exceeded. It also occurs if  
the VREG voltage falls below VREGMON, due to current  
is used to enable the A8450 in response to a high-voltage  
signal, such as from an automobile ignition or battery switch.  
In this capacity, ENBAT is used only as a momentary switch  
to wake up the device. If there is no need for a high-voltage  
signal, ENBAT can be pulled low continuously.  
exceeding IDSLIM  
.
• Both input signal pins, ENB and ENBAT, are pulled low.  
This immediately pulls the NPOR pin low, indicating that  
the device is beginning a power-off sequence. In addition,  
the buck converter switching regulator is disabled, and  
the VREG supply begins to ramp down. The rate at which  
VREG decays is dependent on the total current draw, ILOAD  
and value of the output capacitors (C1, C2, C3, and C4).  
ENB is used to initiate the reset of the device. If ENBAT is  
pulled low, ENB acts as a single reset control.  
,
Diagnostics. An open drain output, through the NFAULT  
pin, is pulled low to signal to a DSP or microcontroller any of  
the following fault conditions:  
• VREG drops below its UVLO threshold, VUVLOVREG  
.
• During any normal power-on, VOUTVADJ falls below  
VUVLOVADJ, triggering a POR.  
• V5A, the 5 V analog regulator output, is shorted to supply  
• Either or both of the V5A and the V5D regulator outputs  
are below their UVLO threshold, VUVLOV5  
An open drain output, through the NPOR pin, is provided to  
signal a POR event to the DSP or microcontroller. The reset  
occurs after an adjustable delay, tPOR, set by an external capaci-  
tor, C9, connected to the CPOR pin. The value of tPOR (ms) is  
calculated using the following formula  
• Device junction temperature, TJ, exceeds the Thermal  
Warning threshold, TJTW  
Charge Pump. The charge pump generates a voltage above  
VBB in order to provide adequate gate drive for the N-channel  
buck switch.A0.1µFceramicmonolithiccapacitor,C7,should  
be connected between the VCP pin and the VBB pin, to act as  
a reservoir to run the buck converter switching regulator.  
tPOR = 2.13 105  
C
CPOR  
× ×  
where CCPOR (µF) is the value of the C9 capacitor.  
VCP is internally monitored to ensure that the charge pump is  
disabled in the case of a fault condition. In addition, a 0.1 µF  
ceramicmonolithiccapacitor,C8,shouldbeconnectedbetween  
CP1 and CP2.  
A POR can be forced without a significant drop in the supply  
voltage, VREG, by pulsing low both the ENB and the ENBAT  
pins. However, pulse duration should be short enough so that  
VREG does not drop significantly.  
Power On Reset Delay. The POR block monitors the sup-  
ply voltages and provides a signal that can be used to reset a  
DSP or microcontroller. A POR event is triggered by any of  
the following conditions:  
Thermal Shutdown. When the device junction temperature,  
TJ, is sensed to be at TJTSD (≈15°C higher than the thermal  
warningtemperature,TJTW), afaultisindicatedattheNFAULT  
pin. At the same time, a thermal shutdown circuit disables the  
buck converter, protecting the A8450 from damage.  
• Either V33 or VADJ is pulled below its UVLO threshold,  
VUVLOV33 or VUVLOVADJ. This occurs if the current limit  
Allegro MicroSystems, Inc.  
9
115 Northeast Cutoff, Box 15036  
A8450KLB-DS, Rev. 1  
Worcester, Massachusetts 01615-0036 (508) 853-5000  
www.allegromicro.com  
1...6789101112...15

中文翻译

下载PDF

A8450KLB-T 替代型号

型号 品牌 替代类型 描述 数据表
A8450KLB-T ALLEGRO

当前型号

 Automotive Analog Circuit, PDSO24
A8450KLBTR-T ALLEGRO

类似代替

 Fixed/Adjustable Positive Standard Regulator, 3 Output, 3.23V1 Min, 1.2V2 Min, 3.366V1 Max

与A8450KLB-T相关器件

型号 品牌 获取价格 描述 数据表
A8450KLBTR ALLEGRO

获取价格

 		Fixed/Adjustable Positive Standard Regulator, 3 Output, 3.23V1 Min, 1.2V2 Min, 3.366V1 Max
A8450KLBTR-T ALLEGRO

获取价格

 		Fixed/Adjustable Positive Standard Regulator, 3 Output, 3.23V1 Min, 1.2V2 Min, 3.366V1 Max
A847CY-100M TOKO

获取价格

 		General Purpose Inductor, 10uH, 20%, 1 Element, SMD
A847CY-120M TOKO

获取价格

 		General Purpose Inductor, 12uH, 20%, 1 Element, SMD
A847CY-150M TOKO

获取价格

 		General Purpose Inductor, 15uH, 20%, 1 Element, SMD
A847CY-180M TOKO

获取价格

 		General Purpose Inductor, 18uH, 20%, 1 Element, SMD
A847CY-1R0M TOKO

获取价格

 		General Purpose Inductor, 1uH, 20%, 1 Element, SMD, 2424
A847CY-1R5M TOKO

获取价格

 		General Purpose Inductor, 1.5uH, 20%, 1 Element, SMD
A847CY-220M TOKO

获取价格

 		General Purpose Inductor, 22uH, 20%, 1 Element, SMD
A847CY-270M TOKO

获取价格

 		General Purpose Inductor, 27uH, 20%, 1 Element, SMD

与A8450KLB-T相关文章

您还可以找


热门产品
PCB打样/小批量
铝基板
BOM智能配单
PCBA制造
钣金
精密CNC
模具注塑
薄膜开关
精选活动
PCBA打样特惠
四六层板品质升级
铝基板品质升级
一体化电子制造
DFM下载
服务支持
企业认证
产品展示
工厂展示
工艺能力
积分商城
关于捷配
捷配简介
企业文化
公司动态
人才招聘
联系我们
帮助中心
下单流程
付款流程
开票流程
常见问题
全球PCB制造服务专线 400-613-0088

工作时间：9:00-21:00

CEO邮箱：ceo@jiepei.com

投诉邮箱：tousu@jiepei.com

捷配网-微信公众号 微信公众号
捷配网-微信公众号 抖音公众号
资质认证：
合作快递：
支付方式：
Copyright © 2024 Jiepei.com Inc. All Rights Reserved. 版权所有:杭州捷配信息科技有限公司 浙公网安备 33010502006866号 浙ICP备10014259号-119 营业执照ICP证