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A8450KLB

更新时间： 2024-01-31 08:40:38
品牌 Logo 应用领域
急速微 - ALLEGRO 线性稳压器IC调节器电源电路光电二极管输出元件
页数 文件大小 规格书
15页 547K
描述
Automotive Multioutput Voltage Regulator

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A8450KLB 技术参数

生命周期：ObsoleteReach Compliance Code：unknown
风险等级：5.84特性阻抗：50 Ω
最大输入功率 (CW)：43.98 dBm最大工作频率：4000 MHz
最小工作频率：最高工作温度：125 °C
最低工作温度：-55 °C射频/微波设备类型：FIXED ATTENUATOR
最大电压驻波比：1.35Base Number Matches：1

A8450KLB 数据手册

 浏览型号A8450KLB的Datasheet PDF文件第5页浏览型号A8450KLB的Datasheet PDF文件第6页浏览型号A8450KLB的Datasheet PDF文件第7页浏览型号A8450KLB的Datasheet PDF文件第9页浏览型号A8450KLB的Datasheet PDF文件第10页浏览型号A8450KLB的Datasheet PDF文件第11页 
A8450  
Automotive Multioutput Voltage Regulator  
short is applied to the regulator output, either V5A or V5D, tors from a short-to-ground condition.The current limit setting,  
the current folds back to 0 V at 50 mA, as shown in figure 4a. ICL (mA), is calculated using the formula  
The voltage recovers to its regulated output when the short is  
removed.  
ICL = VOC ⁄ RRCL  
The V5A and V5D regulators track each other during power- whereRCL(Ω)isthecurrent-limitingresistorcorrespondingto  
on, and when the device is enabled and ramped up out of that regulator (R3 for the 3.3 V regulator, and R4 for the adjust-  
disabled mode, the regulators will start to track when VREG ableregulator).WhenICLisexceeded,themaximumloadcurrent  
reaches approximately 1.8 V. These regulators are guaranteed through that regulator is folded back to 40% of ICL ±10%, as  
to track to within 0.5% of each other under normal operating shown in figure 4b. If current limiting is not needed, the CL33  
conditions.  
and CLADJ pins should be shorted to the VREG pin.  
Disabled Mode. When the two input signal pins, ENBAT  
and ENB, are pulled low, the A8450 enters disabled mode.  
This is a sleep mode, in which all internal circuitry is dis-  
abled in order to draw a minimal current from VBB. When  
either of these pins is pulled high, the device is enabled.  
When emerging from disabled mode, the buck converter  
switching regulator does not operate until the charge pump  
has stabilized (≈300 µs).  
3.3 V and Adjustable Linear Regulators. Two additional  
linear regulators, one that outputs at 3.3 V, and another that has  
a 1.2 V to 3.3 V adjustable output, can be implemented using  
external npn pass transistors. The output voltage of the adjust-  
able regulator, VOUTVADJ (V), is set by the values of the output  
resistors, R1 and R2 (Ω). It can be calculated as  
VOUTVADJ = VFB (1+R1 ⁄ R2)  
where VFB (V) is the voltage on the feedback pin, FB.  
Enabled Mode. When one or both of the signal input  
pins, ENBAT and ENB, are in the high state, the A8450 is  
enabled.  
Additional pins, CL33 and CLADJ, are provided for setting  
currentlimits.Theseareusedtoprotecttheexternalpasstransis-  
5V Regulators Overcurrent Foldback  
3.3 V and Adjustable Regulators Overcurrent Foldback  
6
6
5
4
3
2
5
0.4  
I
10ꢀ  
I
CL  
CL  
4
3
2
1
0
V
and V  
OUTV33  
OUTVADJ(max)  
I
and I  
OUTV5ALIM  
OUTV5DLIM  
V
OUTVADJ(min)  
1
0
200  
250  
300  
0
50  
100  
150  
1600  
0
1600  
IOUT (mA)  
IOUT (mA)  
Figure 4a. Linear foldback to 50 mA. Foldback occurs at the  
typical current limit for the 5 V regulator.  
Figure 4b. Linear foldback to a percentage of ICL. Foldback  
occurs at the current limit setting for the regulator.  
Allegro MicroSystems, Inc.  
8
115 Northeast Cutoff, Box 15036  
A8450KLB-DS, Rev. 1  
Worcester, Massachusetts 01615-0036 (508) 853-5000  
www.allegromicro.com  
1...567891011...15

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