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A8285

更新时间： 2024-02-08 00:25:54
品牌 Logo 应用领域
急速微 - ALLEGRO 稳压器
页数 文件大小 规格书
17页 526K
描述
LNB Supply and Control Voltage Regulator

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A8285 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Obsolete零件包装代码：SOIC
包装说明：BATWING, LEAD FREE, PLASTIC, SOIC-16针数：16
Reach Compliance Code：unknownHTS代码：8542.39.00.01
风险等级：5.81模拟集成电路 - 其他类型：ANALOG CIRCUIT
JESD-30 代码：R-PDSO-G16JESD-609代码：e3
长度：10.21 mm湿度敏感等级：3
功能数量：1端子数量：16
最高工作温度：85 °C最低工作温度：-20 °C
封装主体材料：PLASTIC/EPOXY封装代码：SOP
封装等效代码：SOP16,.4封装形状：RECTANGULAR
封装形式：SMALL OUTLINE峰值回流温度（摄氏度）：NOT SPECIFIED
电源：10/16 V认证状态：Not Qualified
座面最大高度：2.64 mm子类别：Power Management Circuits
最大供电电流 (Isup)：7 mA最大供电电压 (Vsup)：16 V
最小供电电压 (Vsup)：10 V标称供电电压 (Vsup)：12 V
表面贴装：YES温度等级：OTHER
端子面层：Matte Tin (Sn)端子形式：GULL WING
端子节距：1.27 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：7.49 mm
Base Number Matches：1

A8285 数据手册

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A8285/A8287  
LNB Supply and Control Voltage Regulator  
Application Information  
to occur at any time during a data transfer. The A8285/A8287  
Timing Considerations  
always responds by resetting the data transfer sequence.  
The control sequence of the communication through the I2C  
interface is composed of several steps in sequence:  
The Read/Write bit is used to determine the data transfer  
direction. If the Read/Write bit is high, the master reads one  
or more bytes from the A8285/A8287. If the Read/Write bit  
is low, the master writes one byte to the A8285/A8287. Note  
that multiple writes are not permitted. All write operations  
must be preceded with the address.  
1. Start Condition. Defined by a negative edge on the SDA  
line, while SCL is high.  
2. Address Cycle. 7 bits of address, plus 1 bit to indicate  
read (1) or write (0), and an acknowledge bit. The first  
five bits of the address are fixed as: 00010. The four  
optional addresses, defined by the remaining two bits, are  
selected by the ADD input. The address is transmitted  
MSB first.  
The Acknowledge bit has two functions. It is used by the  
master to determine if the slave device is responding to its  
address and data, and it is used by the slave when the master  
is reading data back from the slave. When the A8285/A8287  
decodes the 7-bit address field as a valid address, it responds  
by pulling SDA low during the ninth clock cycle.  
3. Data Cycles. 8 bits of data followed by an acknowledge  
bit. Multiple data bytes can be read. Data is transmitted  
MSB first.  
4. Stop Condition. Defined by a positive edge on the SDA  
line, while SCL is high.  
During a data write from the master, the A8285/A8287 also  
pulls SDA low during the clock cycle that follows the data  
byte, in order to indicate that the data has been successfully  
received. In both cases, the master device must release the  
Except to indicate a Start or Stop condition, SDA must be  
stable while the clock is high. SDA can only be changed  
while SCL is low. It is possible for the Start or Stop condition  
acknowledge  
from LNBR  
acknowledge  
from LNBR  
Writing to the Register  
Start  
Address  
1
W
0
Control Data  
AK D7 D6 D5 D4 D3 D2 D1 D0 AK  
Stop  
SDA  
SCL  
0
1
0
2
0
3
0
5
A1 A0  
4
6
7
8
9
Reading One Byte from the Register  
acknowledge  
from LNBR  
no acknowledge  
from master  
Start  
Address  
1
R
1
Status Data  
Stop  
SDA  
SCL  
0
1
0
2
0
3
0
5
A1 A0  
AK D7 D6 D5 D4 D3 D2 D1 D0 NAK  
4
6
7
8
9
Reading Multiple Bytes from the Register  
acknowledge  
from LNBR  
acknowledge  
from master  
no acknowledge  
from master  
Start  
Address  
1
R
1
Status Data  
Status Data  
Stop  
SDA  
SCL  
0
1
0
2
0
3
0
5
A1 A0  
AK D7 D6 D5 D4 D3 D2 D1 D0 AK D7 D6 D5 D4 D3 D2 D1 D0 NAK  
4
6
7
8
9
8
www.allegromicro.com  
115 Northeast Cutoff, Box 15036  
Worcester, Massachusetts 01615-0036 (508) 853-5000  
1...567891011...17

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