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A80960CA-33 PDF预览

A80960CA-33

更新时间: 2024-02-03 04:35:33
品牌 Logo 应用领域
英特尔 - INTEL 时钟外围集成电路装置
页数 文件大小 规格书
68页 960K
描述
RISC Microprocessor, 32-Bit, 33MHz, MOS, CPGA168, CERAMIC, PGA-168

A80960CA-33 技术参数

生命周期:Obsolete零件包装代码:PGA
包装说明:CERAMIC, PGA-168针数:168
Reach Compliance Code:unknownECCN代码:3A001.A.3
HTS代码:8542.31.00.01风险等级:5.79
其他特性:OPERATING CASE TEMPERATURE 0 TO 100 C地址总线宽度:32
位大小:32边界扫描:NO
最大时钟频率:66.66 MHz外部数据总线宽度:32
格式:FIXED POINT集成缓存:NO
JESD-30 代码:S-CPGA-P168长度:44.7 mm
低功率模式:NODMA 通道数量:4
外部中断装置数量:9串行 I/O 数:
端子数量:168片上数据RAM宽度:8
最高工作温度:100 °C最低工作温度:
封装主体材料:CERAMIC, METAL-SEALED COFIRED封装代码:PGA
封装等效代码:PGA168,17X17封装形状:SQUARE
封装形式:GRID ARRAY电源:5 V
认证状态:Not QualifiedRAM(字数):512
座面最大高度:4.57 mm速度:33 MHz
子类别:Microprocessors最大压摆率:900 mA
最大供电电压:5.25 V最小供电电压:4.75 V
标称供电电压:5 V表面贴装:NO
技术:MOS温度等级:OTHER
端子形式:PIN/PEG端子节距:2.54 mm
端子位置:PERPENDICULAR宽度:44.7 mm
uPs/uCs/外围集成电路类型:MICROPROCESSOR, RISCBase Number Matches:1

A80960CA-33 数据手册

 浏览型号A80960CA-33的Datasheet PDF文件第2页浏览型号A80960CA-33的Datasheet PDF文件第3页浏览型号A80960CA-33的Datasheet PDF文件第4页浏览型号A80960CA-33的Datasheet PDF文件第6页浏览型号A80960CA-33的Datasheet PDF文件第7页浏览型号A80960CA-33的Datasheet PDF文件第8页 
80960CA-33, -25, -16  
A
32-bit demultiplexed and pipelined burst bus  
1.0 PURPOSE  
provides a 132 Mbyte/s bandwidth to a system’s  
high-speed external memory sub-system. In  
addition, the 80960CA’s on-chip caching of instruc-  
tions, procedure context and critical program data  
substantially decouple system performance from the  
wait states associated with accesses to the system’s  
slower, cost sensitive, main memory subsystem.  
This document provides electrical characteristics for  
the 33, 25 and 16 MHz versions of the 80960CA. For  
a detailed description of any 80960CA functional  
topic—other than parametric performance—consult  
the 80960CA Product Overview (Order No. 270669)  
or the i960 CA Microprocessor User’s Manual  
(Order No. 270710). To obtain data sheet updates  
and errata, please call Intel’s FaxBACK data-on-  
demand system (1-800-628-2283 or 916-356-3105).  
Other information can be obtained from Intel’s tech-  
nical BBS (916-356-3600).  
The 80960CA bus controller integrates full wait state  
and bus width control for highest system perfor-  
mance with minimal system design complexity.  
Unaligned access and Big Endian byte order support  
reduces the cost of porting existing applications to  
the 80960CA.  
2.0 80960CA OVERVIEW  
The processor also integrates four complete data-  
chaining DMA channels and a high-speed interrupt  
controller on-chip. DMA channels perform: single-  
cycle or two-cycle transfers, data packing and  
unpacking and data chaining. Block transfers—in  
addition to source or destination synchronized trans-  
fers—are provided.  
The 80960CA is the second-generation member of  
the 80960 family of embedded processors. The  
80960CA is object code compatible with the 32-bit  
80960 Core Architecture while including Special  
Function Register extensions to control on-chip  
peripherals and instruction set extensions to shift 64-  
bit operands and configure on-chip hardware.  
Multiple 128-bit internal buses, on-chip instruction  
caching and a sophisticated instruction scheduler  
allow the processor to sustain execution of two  
instructions every clock and peak at execution of  
three instructions per clock.  
The interrupt controller provides full programmability  
of 248 interrupt sources into 32 priority levels with a  
typical interrupt task switch (”latency”) time of  
750 ns.  
DMA  
DMA Controller Port  
Instruction Prefetch Queue  
Four-Channel  
Instruction Cache  
(1 KByte, Two-way  
Set Associative)  
Control  
Memory Region  
Configuration  
128-BIT CACHE BUS  
Bus  
Interrupt  
Port  
Programmable  
Interrupt Controller  
Controller  
Parallel  
Address  
Data  
Instruction  
Scheduler  
Bus Request  
Queues  
Multiply/Divide  
Unit  
1 KByte  
Data RAM  
Register-side  
Machine Bus  
Memory-side  
Machine Bus  
Execution  
Unit  
5 to 15 Sets  
Register Cache  
Six-port  
Register File  
Address  
Generation Unit  
64-Bit  
32-Bit  
SRC1 Bus  
Base Bus  
64-Bit  
SRC2 Bus  
128-Bit  
Load Bus  
64-Bit  
DST Bus  
128-Bit  
Store Bus  
F_CX001A  
Figure 1. 80960CA Block Diagram  
1

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