Datasheet > 存储 > SRAM> A63P73361E-6.5F

A63P73361E-6.5F

更新时间： 2024-02-26 08:27:03

品牌	Logo	应用领域
联笙电子 - AMICC		计数器存储静态存储器
页数	文件大小	规格书
16页	263K
描述
128K X 36 Bit Synchronous High Speed SRAM with Burst Counter and Flow-through Data Output

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技术参数
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A63P73361E-6.5F 技术参数

生命周期：	Contact Manufacturer	包装说明：	,
Reach Compliance Code：	unknown	风险等级：	5.8
Base Number Matches：	1

A63P73361E-6.5F 数据手册

A63P73361

128K X 36 Bit Synchronous High Speed SRAM with

Burst Counter and Flow-through Data Output

Preliminary

Features

ꢀFast access times: 6.5/7.5/8.0 ns(153/133/117 MHz)

ꢀSingle 2.5V±5% power supply

ꢀSynchronous burst function

ꢀIndividual Byte Write control and Global Write

ꢀThree separate chip enables allow wide range of

options for CE control, address pipelining

ꢀSelectable BURST mode

ꢀSLEEP mode (ZZ pin) provided

ꢀAvailable in 100-pin LQFP package

ꢀIndustrial operating temperature range: -45°C to

+125°C for -I series

General Description

The A63P73361 is a high-speed SRAM containing 4.5M

bits of bit synchronous memory, organized as 128K

words by 36 bits.

The A63P73361 combines advanced synchronous

peripheral circuitry, 2-bit burst control, input registers,

output buffer and a 128K X 36 SRAM core to provide a

wide range of data RAM applications.

The positive edge triggered single clock input (CLK)

controls all synchronous inputs passing through the

registers. Synchronous inputs include all addresses (A0 -

A16), all data inputs (I/O¹- I/O36), active LOW chip enable

Burst operations can be initiated with either the address

status processor ( ADSP ) or address status controller

( ADSC ) input pin. Subsequent burst sequence burst

addresses can be internally generated by the A63P73361

and controlled by the burst advance ( ADV ) pin. Write

cycles are internally self-timed and synchronous with the

rising edge of the clock (CLK).

This feature simplifies the write interface. Individual Byte

enables allow individual bytes to be written. BW1 controls

I/O¹- I/O9, BW2 controls I/O10 - I/O18, BW3 controls

I/O¹⁹- I/O27, and BW4 controls I/O28 - I/O36, all on the

( CE ), two additional chip enables (CE2, CE2 ), burst

control inputs ( ADSC , ADSP , ADV ), byte write enables

( BWE , BW1 , BW2 , BW3 , BW4 ) and Global Write

condition that BWE is LOW. GW LOW causes all bytes

to be written.

( GW ). Asynchronous inputs include output enable ( OE ),

clock (CLK), BURST mode (MODE) and SLEEP mode

(ZZ).

PRELIMINARY

(July, 2005, Version 0.0)

AMIC Technology, Corp.

123 4 5 6 7...16

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