Datasheet > A62S8308M-55S

A62S8308M-55S

更新时间： 2022-01-13 11:31:17

品牌	Logo	应用领域
联笙电子 - AMICC		静态存储器
页数	文件大小	规格书
17页	266K
描述
256K X 8 BIT LOW VOLTAGE CMOS SRAM

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数据手册

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A62S8308M-55S 数据手册

A62S8308 Series

AC Characteristics (TA = 0°C to + 70°C or -25°C to 85°C, VCC = 2.7V to 3.6V)

Symbol

Parameter

A62S8308-55S/SI

A62S8308-70S/SI

Unit

(VCC = 3.0V to 3.6V) (VCC = 2.7V to 3.6V)

Min.

Max.

Min.

Max.

Read Cycle

tRC

Read Cycle Time

tAA

Address Access Time

tACE1

Chip Enable Access Time

CE1

CE2

tACE2

tOE

Output Enable to Output Valid

Chip Enable to Output in Low Z

tCLZ1

CE1

CE2

tCLZ2

tOLZ

Output Enable to Output in Low Z

Chip Disable to Output in High Z

tCHZ1

CE1

CE2

tCHZ2

tOHZ

Output Disable to Output in High Z

Output Hold from Address Change

tOH

Read Cycle

tWC

Write Cycle Time

tCW

Chip Enable to End of Write

Address Setup Time

tAS

tAW

Address Valid to End of Write

Write Pulse Width

tWP

tWR

Write Recovery Time

tWHZ

tDW

Write to Output in High Z

Data to Write Time Overlap

Data Hold from Write Time

Output Active from End of Write

tDH

tOW

Notes: tCHZ1, tCHZ2, tOHZ and tWHZ are defined as the time at which the outputs achieve the open circuit condition and are

not referred to output voltage levels.

PRELIMINARY

(March, 2001, Version 0.2)

AMIC Technology, Inc.

1...3 4 567 8 9...17

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与A62S8308M-55S相关器件

型号	品牌	描述	获取价格	数据表
A62S8308M-55SI	AMICC	256K X 8 BIT LOW VOLTAGE CMOS SRAM	获取价格
A62S8308M-70S	AMICC	256K X 8 BIT LOW VOLTAGE CMOS SRAM	获取价格
A62S8308M-70SI	AMICC	256K X 8 BIT LOW VOLTAGE CMOS SRAM	获取价格
A62S8308V-55S	AMICC	256K X 8 BIT LOW VOLTAGE CMOS SRAM	获取价格
A62S8308V-55SI	AMICC	256K X 8 BIT LOW VOLTAGE CMOS SRAM	获取价格
A62S8308V-70S	AMICC	256K X 8 BIT LOW VOLTAGE CMOS SRAM	获取价格