A61L6316V-15I

更新时间： 2024-01-09 23:03:53

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A61L6316V-15I 数据手册

A61L6316 Series

Timing Waveforms

Read Cycle 1^{(1, 2, 4)}

tRC

Address

tAA

tOH

DOUT

Read Cycle 2^{(1, 2, 3)}

tRC

Address

tAA

tACE

tCHZ

tCLZ

tBE

HB, LB

tBLZ

tBHZ

tOE

tOHZ

tOLZ

DOUT

Notes: 1. WE is high for Read Cycle.

2. Device is continuously enabled CE = VIL, HB = VIL and, or LB = VIL.

3. Address valid prior to or coincident with CE and (HB and, or LB ) transition low.

4. OE = VIL.

5. Transition is measured ±200mV from steady state. This parameter is sampled and not 100% tested.

(July, 2002, Version 1.1)

AMIC Technology, Inc.

1...5 6 789 10 11...15

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