Datasheet > A4J-L67202V-60

A4J-L67202V-60

更新时间： 2024-01-04 10:10:58

品牌	Logo	应用领域
TEMIC		先进先出芯片
页数	文件大小	规格书
16页	146K
描述
FIFO, 1KX9, 60ns, Asynchronous, CMOS, LCC-32

阅读下载

获取价格

技术参数
数据手册

如果您发现信息不准确，欢迎纠错

A4J-L67202V-60 技术参数

生命周期：	Transferred	包装说明：	LCC-32
Reach Compliance Code：	unknown	风险等级：	5.78
最长访问时间：	60 ns	周期时间：	75 ns
JESD-30 代码：	S-XQCC-N32	内存密度：	9216 bit
内存宽度：	9	功能数量：	1
端子数量：	32	字数：	1024 words
字数代码：	1000	工作模式：	ASYNCHRONOUS
最高工作温度：	125 °C	最低工作温度：	-40 °C
组织：	1KX9	可输出：	NO
封装主体材料：	UNSPECIFIED	封装形状：	SQUARE
封装形式：	CHIP CARRIER	并行/串行：	PARALLEL
认证状态：	Not Qualified	最大供电电压 (Vsup)：	3.6 V
最小供电电压 (Vsup)：	3 V	标称供电电压 (Vsup)：	3.3 V
表面贴装：	YES	技术：	CMOS
温度等级：	AUTOMOTIVE	端子形式：	NO LEAD
端子位置：	QUAD	Base Number Matches：	1

A4J-L67202V-60 数据手册

MATRA MHS

L 67201/L 67202

single word to be read after one word has been written to In the write flow-through mode (figure 18), the FIFO

an empty FIFO stack. The data is enabled on the bus at stack allows a single word of data to be written

(tWEF + tA) ns after the leading edge of W which is immediately after a single word of data has been read

known as the first write edge and remains on the bus until from a full FIFO stack. The R line causes the FF to be

the R line is raised from low to high, after which the bus reset, but the W line, being low, causes it to be set again

will go into a three-state mode after tRHZ ns. The EF line in anticipation of a new data word. The new word is

will show a pulse indicating temporary reset and then will loaded into the FIFO stack on the leading edge of W. The

be set. In the interval in which R is low, more words may W line must be toggled when FF is not set in order to write

be written to the FIFO stack (the subsequent writes after new data into the FIFO stack and to increment the write

the first write edge will reset the Empty Flag) ; however, pointer.

the same word (written on the first write edge) presented

to the output bus as the read pointer will not be

incremented if R is low. On toggling R, the remaining

words written to the FIFO will appear on the output bus

in accordance with the read cycle timings.

Figure 4. Block Diagram of 1536 × 9 / 3072 × 9 FIFO Memory (Depth expansion).

67201/202

FULL

EMPTY

67201/202

Figure 5. Compound FIFO Expansion.

– Q

(N–8)

– Q

(N–8)

L 67201/202

R . W . RS

DEPTH

EXPANSION

BLOCK

DEPTH

EXPANSION

BLOCK

DEPTH

EXPANSION

BLOCK

– I

(N–8)

– I

I – I

(N–8) N

Notes : 6. For depth expansion block see section on Depth Expansion and Figure 4.

7. For Flag detection see section on Width Expansion and Figure 3.

Rev. C (10/11/95)

1...4 5 678 9 10...16

下载PDF

与A4J-L67202V-60相关器件

型号	品牌	描述	获取价格	数据表
A4J-L67202V-65	TEMIC	FIFO, 1KX9, 65ns, Asynchronous, CMOS, LCC-32	获取价格
A4K102-RB-10	SUPERWORLD	FERRITE CHIP BEADS 4 LINE ARRAY	获取价格
A4K121-RD-10	SUPERWORLD	FERRITE CHIP BEADS 4 LINE ARRAY	获取价格
A4K300-RE-10	SUPERWORLD	FERRITE CHIP BEADS 4 LINE ARRAY	获取价格
A4K301-RC-10	SUPERWORLD	FERRITE CHIP BEADS 4 LINE ARRAY	获取价格
A4K600-RD-10	SUPERWORLD	FERRITE CHIP BEADS 4 LINE ARRAY	获取价格

与A4J-L67202V-60相关文章

SG3525资料手册详解：SG3525参数分析、引脚说明、应用介绍
2024-05-23

5
AT89C51单片机资料手册详细解析及应用示例
2024-05-23

8
CP2102资料手册解读：CP2102引脚说明、关键参数分析
2024-05-23

4
资料手册解读：UC3842参数和管脚说明
2024-05-22

6

产品中心

服务支持

精选活动

关于我们

帮助中心

A4J-L67202V-60

A4J-L67202V-60 技术参数

A4J-L67202V-60 数据手册

与A4J-L67202V-60相关器件

与A4J-L67202V-60相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

A4J-L67202V-60

A4J-L67202V-60 技术参数

A4J-L67202V-60 数据手册

与A4J-L67202V-60相关器件

与A4J-L67202V-60相关文章

您还可以找

您在本页遇到什么问题？