Datasheet > A4K-L67132L-45

A4K-L67132L-45

更新时间： 2022-12-01 23:20:38

品牌	Logo	应用领域
TEMIC		静态存储器
页数	文件大小	规格书
14页	178K
描述
Dual-Port SRAM, 2KX8, 45ns, CMOS, LCC-48

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A4K-L67132L-45 数据手册

L67132/L67142

2 K × 8 CMOS Dual Port RAM 3.3 Volt

Introduction

The L67132/67142 are very low power CMOS dual port Using an array of eight transistors (8T) memory cell and

static RAMs organized as 2048 × 8. They are designed to fabricated with the state of the art 1.0 µm lithography

be used as a stand-alone 8 bit dual port RAM or as a named SCMOS, the L67132/67142 combine an

combination MASTER/SLAVE dual port for 16 bits or extremely low standby supply current (typ = 1.0 µA) with

more width systems. The MHS MASTER/SLAVE dual a fast access time at 45 ns over the full temperature range.

port approach in memory system applications results in All versions offer battery backup data retention capability

full speed, error free operation without the need for with a typical power consumption at less than 5 µW.

additional discrete logic.

For military/space applications that demand superior

Master and slave devices provide two independent ports

with separate control, address and I/O pins that permit

independent, asynchronous access for reads and writes to

any location in the memory. An automatic power down

feature controlled by CS permits the onchip circuitry of

each port in order to enter a very low stand by power

mode.

levels of performance and reliability the L67132/67142

is processed according to the methods of the latest

revision of the MIL STD 883 (class B or S) and/or ESA

SCC 9000.

Features

D Single 3.3 V ± 0.3 volt power supply

D Fast access time

D On chip arbitration logic

D BUSY output flag on master

D BUSY input flag on slave

D Fully asynchronous operation from either port

D Battery backup operation :

2 V data retention

45(*) ns to 70 ns

D 67132L/67142L low power

67132V/67142V very low power

D Expandable data bus to 16 bits or more using master/slave

devices when using more than one device

(*) Preliminary

MATRA MHS

Rev. D (19 Fev. 97)

12 3 4 5 6 7...14

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