Datasheet > A4919GETTR-5-T

A4919GETTR-5-T

更新时间： 2022-05-14 22:19:46

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急速微 - ALLEGRO		/
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22页	956K
描述
Three-Phase MOSFET Driver with Integrated Regulator

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数据手册

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A4919GETTR-5-T 数据手册

Three-Phase MOSFET Driver

with Integrated Regulator

A4919

ELECTRICAL CHARACTERISTICS ^[1](continued): Valid at T_J= 25°C, V_BB= 7 to 50 V, unless otherwise specified

Characteristic

LOGIC INPUTS AND OUTPUTS

Input Low Voltage

Symbol

Test Conditions

Min.

Typ.

Max.

Unit

V_IL

V_IH

–

2.0

100

–

0.8

–

Input High Voltage

Input Hysteresis

V_Ihys

R_PD

t_PIN

300

–

kΩ

Input Pull-Down Resistor (xHI, xLO)

Input Pulse Filter Time (xHI, xLO)

VDS Disable Voltage

–

V_DSD

V_FLTD

V_OL

I_O

–

100

0.5

0.4

Fault Disable Voltage

–

Output Low Voltage (FAULT)

Output Leakage (FAULT) ^[5]

PROTECTION

I_OL= 1 mA, no fault indicated

0 V < V_O< 5.5 V, fault indicated

–

0.2

–

–1

µA

V_REGONVREG rising

V_REGOFFVREG falling

V_BOOTUVVBOOT falling, VCx – VSx

V_BOOTHys

7.5

6.75

7.25

–

8.5

7.75

VREG Undervoltage Lockout

Bootstrap Undervoltage Threshold

Bootstrap Undervoltage Hysteresis

%V_REG

–

VDDM / V3 / V5 Undervoltage

Threshold ^[6]

V_DDUV

Voltage falling

2.45

2.7

2.85

160

VDDM / V3 / V5 Undervoltage

Hysteresis ^[6]

V_DDUVHys

100

VDS Threshold – Internal

VDS Threshold Range

VDS Threshold Input Leakage

VBRG Input Voltage

V_DSTHI

V_DSTH

V_DSTHL

V_BRG

V_DSTH> 2.7 V

1.0

0.2

– 3

V_BB– 1

–

1.2

–

1.4

0 V < V_DSTH< 5.5 V

–

µA

V_BB

–

V_BB+ 1

250

–

VBRG Input Current

I_VBRG

V_DSTH= 2 V, V_BB= 12 V, 0 V < V_BRG< V_BB

µA

µs

V_DSTH≥ 1 V

–

±100

±50

±100

±50

2.3

–

Short-to-Ground Threshold Offset

V_STGO

_DSTH< 1 V

V_DSTH≥ 1 V

_DSTH< 1 V

–150

–

+150

–

Short-to-Power Supply Threshold

Offset

V_STPO

–150

1.5

170

–

+150

4.5

180

–

VDS Fault Blank Time

t_BL

T_JF

Overtemperature Warning

Overtemperature Hysteresis

Temperature increasing

Recovery = T_JF– T_JHyst

°C

T_JHyst

VARIANT WITHOUT LDO REGULATOR ONLY (A4919x)

Input Low Voltage For Sleep Mode

V_ILS

t_SLT

xHI, xLO

–

0.5

Sleep Mode Activation Timeout

(xHI, xLO) ^[3]

From all xHI, xLO < V_IL

Any xHI, xLO > V_IH, C_REG< 1 µF

7.5

12.5

Wake-up from Sleep Delay ^[3]

Gate Drive Disable Threshold

VDDM Pull-Down Resistor

t_WK

–

V_GDD

R_VDDM

1.5

kΩ

Continued on the next page…

Allegro MicroSystems, LLC

955 Perimeter Road

Manchester, NH 03103-3353 U.S.A.

www.allegromicro.com

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