A48P3616A
Pin Descriptions
Symbol
Type
Description
Clock: CK and CK are differential clock inputs. All address and control input signals
are sampled on the crossing of the positive edge of CK and negative edge of CK.
Input
CK, CK
CK
Output (read) data is referenced to the crossings of CK and
crossing).
(both directions of
Clock Enable: CKE HIGH activates, and CKE Low deactivates, internal clock
signals and device input buffers and output drivers. Taking CKE Low provides
Precharge Power Down and Self Refresh operation (all banks idle), or Active Power
Down (row Active in any bank). CKE is synchronous for power down entry and exit,
and for self refresh entry. CKE is asynchronous for self refresh exit. CKE must be
maintained high throughout read and write accesses. Input buffers, excluding CK,
CKE
Input
CK
and CKE are disabled during Power Down. Input buffers, excluding CKE, are
disabled during self refresh.
Chip Select: All commands are masked when CS is registered high. CS provides
Input
Input
CS
for external bank selection on systems with multiple banks. CS is considered part of
the command code.
Command Inputs: RAS , CAS , WE (along with CS ) define the command being
entered.
RAS , CAS , WE
Input Data Mask: DM is an input mask signal for write data. Input data is masked
when DM is sampled high coincident with that input data during a Write access. DM
is sampled on both edges of DQS. Although DM pins are input only, the DM loading
matches the DQ and DQS loading. During a Read, DM can be driven high, low, or
floated. LDM corresponds to the data on DQ0-DQ7; UDM corresponds to the data on
DQ8-DQ15.
UDM, LDM
BA0, BA1
Input
Input
Bank Address Inputs: BA0 and BA1 define to which bank an Active, Read, Write or
Precharge command is being applied. BA0 and BA1 also determines if the mode
register or extended mode register is to be accessed during a MRS or EMRS cycle.
Address Inputs: Provide the row address for Active commands, and the column
address and Auto Precharge bit for Read/Write commands, to select one location
out of the memory array in the respective bank. A10 is sampled during a Precharge
command to determine whether the Precharge applies to one bank (A10 low) or all
banks (A10 high). If only one bank is to be precharged, the bank is selected by BA0,
BA1. The address inputs also provide the op-code during a Mode Register Set
command.
A0-A11
Input
DQ
Input / Output Data Input/Output: Data bus.
Data Strobe: Output with read data, input with write data. Edge-aligned with read
LDQS, UDQS
Input / Output data, centered in write data. Used to capture write data. LDQS corresponds to the
data on DQ0-DQ7; UDQS corresponds to the data on DQ8-DQ15
NC
No Connect: No internal electrical connection is present.
DQ Power Supply: 2.5V ± 0.2V.
DQ Ground
VDDQ
VSSQ
VDD
Supply
Supply
Supply
Supply
Supply
Power Supply: 2.5V ± 0.2V.
Ground
VSS
SSTL_2 reference voltage: (VDDQ / 2) ± 1%.
VREF
PRELIMINARY (July, 2010, Version 0.0)
4
AMIC Technology, Corp.
5秒后页面跳转
资料手册解读：UC3842参数和管脚说明
一文带你了解无源晶振的负载电容为何要加两颗谐振电容CL1和CL2
玻璃管保险丝与陶瓷管保险丝：区别与替代性探讨
PCF8574资料解读：主要参数分析、引脚说明
微信公众号
抖音公众号
浙公网安备 33010502006866号 浙ICP备10014259号-119
营业执照ICP证
技术参数
数据手册
如果您发现信息不准确，
