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A4403GEU-T

更新时间： 2024-01-11 14:20:14

品牌	Logo	应用领域
急速微 - ALLEGRO		转换器稳压器开关式稳压器或控制器电源电路开关式控制器
页数	文件大小	规格书
15页	335K
描述
Valley Current Mode Control Buck Converter

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技术参数
数据手册

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A4403GEU-T 技术参数

是否无铅：	不含铅	是否Rohs认证：	符合
生命周期：	Active	零件包装代码：	QFN
包装说明：	HVQCCN, LCC16,.16SQ,25	针数：	16
Reach Compliance Code：	compliant	ECCN代码：	EAR99
HTS代码：	8542.39.00.01	风险等级：	1.69
模拟集成电路 - 其他类型：	SWITCHING REGULATOR	控制模式：	CURRENT-MODE
控制技术：	PULSE FREQUENCY MODULATION	最大输入电压：	46 V
最小输入电压：	9 V	JESD-30 代码：	S-XQCC-N16
JESD-609代码：	e3	长度：	4 mm
湿度敏感等级：	2	功能数量：	1
端子数量：	16	最高工作温度：	105 °C
最低工作温度：	-40 °C	最大输出电流：	4.2 A
封装主体材料：	UNSPECIFIED	封装代码：	HVQCCN
封装等效代码：	LCC16,.16SQ,25	封装形状：	SQUARE
封装形式：	CHIP CARRIER	峰值回流温度（摄氏度）：	260
认证状态：	Not Qualified	座面最大高度：	0.8 mm
子类别：	Switching Regulator or Controllers	表面贴装：	YES
切换器配置：	BUCK	最大切换频率：	2000 kHz
温度等级：	INDUSTRIAL	端子面层：	Matte Tin (Sn)
端子形式：	NO LEAD	端子节距：	0.65 mm
端子位置：	QUAD	处于峰值回流温度下的最长时间：	40
宽度：	4 mm	Base Number Matches：	1

A4403GEU-T 数据手册

Valley Current Mode Control Buck Converter

A4403

current, with perhaps some margin to allow for overloads, and

so forth.

to reduce the bandwidth and therefore compromise the transient

response performance.

• saturation current. The worst case maximum peak current

should not exceed the saturation current and indeed some mar-

gin should be allowed. The maximum peak current can be found

to ensure the saturation current level of the chosen inductor is

not exceeded:

In general the output capacitance should not exceed 1000 ꢀF or

be less than 10 ꢀF, as this may cause a loop instability to occur.

The output ripple is largely determined by the output capacitance,

and the effects of ESR and ESL can largely be ignored assum-

ing good layout practice is observed. To help reduce the effects

of ESL it is a good idea to split the 20 ꢀF capacitance into two

separate 10 ꢀF components.

I_RIPPLE

(11)

I_sat= I_LOAD

It is important to ensure that, under worst-case conditions (mini-

mum input voltage, maximum load current, minimum inductance,

and minimum switching frequency), that the minimum current

limit is not exceeded and in fact has some margin. The current

limit is measured at the valley level. The maximum current at the

valley is found from:

The output voltage ripple can be approximated to:

I_RIPPLE

(13)

V_RIPPLE

≈

8 × f_SW× C_OUT

where I_RIPPLEis as found in the Inductor section.

When using ceramic capacitors, due to the negligible heating

I_RIPPLE

(12)

effects of the ESR, there is generally no need to consider the cur-

rent carrying capability. Also, the RMS current flowing into the

output capacitor is extremely low.

I_valley= I_LOAD

–

The minimum current limit threshold should be at least 20%

above this level.

Input Capacitor It is recommended that ceramic X5R or X7R

capacitors be used, or at least that they be used in conjunction

with some other capacitor technology; for example, aluminum

electrolytic. Note that the self-resonance of electrolytics tend to

occur in the 100s of kHz, therefore the effects of ESL become

apparent at switching frequencies in the region of 1 MHz.

Recommended inductor manufacturers and ranges are:

• Tayo Yuden: NR6045 series

• Sumida: CDR7D43MN series

Output Capacitor In the interests of size, cost, and perfor-

mance, this control architecture has been designed for ceramic

capacitors. It is imperative that ceramic X5R or X7R capacitors

are used. On no account should Y5V, Y5U, Z5U, or similar types

be used.

The value of the input capacitance determines the amount of

ripple voltage that appears at the source terminals. If a system is

designed correctly, the input capacitor should supply the switch-

ing current minus the input average current during the on-time of

the power switch. During the off-time of the power switch, the

input capacitor is charged-up.

When using ceramic capacitors, another important consider-

ation is the E-field effects on the actual value of the capacitor.

To minimize the effects of the capacitance being reduced with

output voltage, it is recommended that the working voltage of the

capacitor be considerably more than the set output voltage. Check

with the vendor to obtain this information.

The RMS current that flows in the input capacitor can be found

from:

1/2

⎛

⎞

V_IN

I_OUT× V_OUT

⎜

⎟

–

I_rms

(14)

V_OUT

V_IN

The output capacitor determines the output voltage ripple and is

used to close the control loop. As outlined in the Control Loop

section, the bandwidth has been optimized for an output capaci-

tance of 20 ꢀF.

⎝

⎠

The amount of ripple voltage that appears across the input termi-

nals depends on: the amount of charge removed during the switch

on-time and the actual capacitor value. If a capacitor technology

such as an electrolytic is used, then the effects of ESR also have

If a particular application requires an extremely low output volt-

age, the output capacitor can be increased. Any increase will tend to be considered.

Allegro MicroSystems, Inc.

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

1...6 7 8910 11 12...15

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