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A43P26161V-75UF PDF预览

A43P26161V-75UF

更新时间: 2024-02-10 22:34:25
品牌 Logo 应用领域
联笙电子 - AMICC 存储动态存储器
页数 文件大小 规格书
44页 1122K
描述
1M X 16 Bit X 4 Banks Low Power Synchronous DRAM

A43P26161V-75UF 技术参数

生命周期:Contact Manufacturer包装说明:,
Reach Compliance Code:unknown风险等级:5.75
Is Samacsys:NBase Number Matches:1

A43P26161V-75UF 数据手册

 浏览型号A43P26161V-75UF的Datasheet PDF文件第1页浏览型号A43P26161V-75UF的Datasheet PDF文件第3页浏览型号A43P26161V-75UF的Datasheet PDF文件第4页浏览型号A43P26161V-75UF的Datasheet PDF文件第5页浏览型号A43P26161V-75UF的Datasheet PDF文件第6页浏览型号A43P26161V-75UF的Datasheet PDF文件第7页 
A43P26161  
Preliminary  
1M X 16 Bit X 4 Banks Low Power Synchronous DRAM  
Features  
Low power supply  
64ms refresh period (4K cycle)  
- VDD: 2.5V VDDQ : 2.5V  
Self refresh with programmable refresh period through  
LVCMOS compatible with multiplexed address  
EMRS cycle  
Programmable Power Reduction Feature by partial  
array activation during Self-refresh through EMRS  
cycle  
Industrial operating temperature range: -40ºC to +85ºC  
for -U series.  
Available in 54 Balls CSP (8mm X 8mm) and 54-pin  
TSOP(II) packages.  
Package is available to lead free (-F series)  
Four banks / Pulse RAS  
MRS cycle with address key programs  
- CAS Latency (2 & 3)  
- Burst Length (1,2,4,8 & full page)  
- Burst Type (Sequential & Interleave)  
All inputs are sampled at the positive going edge of the  
system clock  
Deep Power Down Mode  
DQM for masking  
Auto & self refresh  
Clock Frequency (max) : 105MHz @ CL=3 (-95)  
133MHz @ CL=3 (-75)  
General Description  
The A43P26161 is 67,108,864 bits Low Power  
synchronous high data rate Dynamic RAM organized as 4  
X 1,048,576 words by 16 bits, fabricated with AMIC’s high  
performance CMOS technology. Synchronous design  
allows precise cycle control with the use of system clock.  
I/O transactions are possible on every clock cycle. Range  
of operating frequencies, programmable latencies allows  
the same device to be useful for a variety of high  
bandwidth,  
high  
performance  
memory  
system  
applications.  
Pin Configuration  
54 Balls CSP (8 mm x 8 mm)  
Top View  
54 Ball (6X9) CSP  
1
2
3
7
8
9
A
B
C
D
E
F
VSS  
DQ15  
DQ13  
DQ11  
DQ9  
NC  
VSSQ  
VDDQ  
VSSQ  
VDDQ  
VSS  
VDDQ  
VSSQ  
VDDQ  
VSSQ  
VDD  
DQ0  
DQ2  
VDD  
DQ1  
DQ3  
DQ5  
DQ7  
DQ14  
DQ12  
DQ10  
DQ8  
DQ4  
DQ6  
LDQM  
UDQM  
CLK  
CKE  
CAS  
BA0  
RAS  
BA1  
WE  
G
NC  
A11  
A9  
CS  
A10  
VDD  
H
J
A8  
A7  
A5  
A6  
A4  
A0  
A3  
A1  
A2  
VSS  
PRELIMINARY  
(July, 2005, Version 1.1)  
1
AMIC Technology, Corp.  

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