Datasheet > A43L4608AV-75F

A43L4608AV-75F

更新时间： 2024-02-20 22:51:51

品牌	Logo	应用领域
联笙电子 - AMICC		动态存储器
页数	文件大小	规格书
40页	591K
描述
DRAM

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技术参数
数据手册

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A43L4608AV-75F 技术参数

生命周期：	Contact Manufacturer	包装说明：	,
Reach Compliance Code：	unknown	风险等级：	5.75
Base Number Matches：	1

A43L4608AV-75F 数据手册

A43L3616A/A43L4608A

Pin Descriptions

Symbol

Name

Description

CLK

System Clock

Chip Select

Active on the positive going edge to sample all inputs.

Disables or Enables device operation by masking or enabling all inputs except CLK,

CKE and L(U)DQM

Masks system clock to freeze operation from the next clock cycle.

CKE should be enabled at least one clock + tss prior to new command.

Disable input buffers for power down in standby.

CKE

Clock Enable

Row / Column addresses are multiplexed on the same pins.

Row address : RA0~RA11, Column address: CA0~CA8 (x16) or CA0~CA9 (x8)

Selects bank to be activated during row address latch time.

Selects band for read/write during column address latch time.

A0~A11

Address

BA0, BA1

Bank Select Address

Row Address Strobe

Latches row addresses on the positive going edge of the CLK with RAS low.

Enables row access & precharge.

RAS

Latches column addresses on the positive going edge of the CLK with CAS low.

Enables column access.

Column Address

Strobe

CAS

Write Enable

Enables write operation and Row precharge.

Makes data output Hi-Z, tSHZ after the clock and masks the output.

Blocks data input when L(U)DQM active.

DQM,

Data Input/Output

Mask

DQM corresponds to DQ⁰~ DQ7 (A43L4608A).

L(U)DQM

LDQM corresponds to DQ0 ~ DQ7, UDQM corresponds to DQ8 ~ DQ15 (A43L3616A)

Data inputs/outputs are multiplexed on the same pins.

DQ0-15

Data Input/Output

Power

Supply/Ground

VDD/VSS

Power Supply: +3.3V±0.3V/Ground

Data Output

Power/Ground

VDDQ/VSSQ

NC/RFU

Provide isolated Power/Ground to DQs for improved noise immunity.

No Connection

PRELIMINARY (May, 2008, Version 0.3)

AMIC Technology, Corp.

1 2 3 456 7 8...40

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