Datasheet > A43L3632V-95I

A43L3632V-95I

更新时间： 2022-04-25 03:52:45

品牌	Logo	应用领域
联笙电子 - AMICC		动态存储器
页数	文件大小	规格书
42页	502K
描述
1M X 16 Bit X 4 Banks Synchronous DRAM

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A43L3632V-95I 数据手册

A43L2616B

Operating AC Parameter

(AC operating conditions unless otherwise noted)

Version

Symbol

Parameter

Unit

Note

-6

-7

tRRD(min)

tRCD(min)

Row active to row active delay

RAS to

delay

CAS

tRP(min)

tRAS(min)

tRAS(max)

tRC(min)

Row precharge time

Row active time

μs

100

Row cycle time

tCDL(min)

tRDL(min)

tBDL(min)

tCCD(min)

Last data in new col. Address delay

Last data in row precharge

Last data in to burst stop

Col. Address to col. Address delay

CAS Latency = 3

CAS Latency = 2

Number of valid output data

Note: 1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and

then rounding off to the next higher integer.

2. Minimum delay is required to complete write.

3. In case of row precharge interrupt, auto precharge and read burst stop.

(December, 2009, Version 1.3)

AMIC Technology, Corp.

1...5 6 789 10 11...42

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