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A43L3616V-7V PDF预览

A43L3616V-7V

更新时间: 2024-02-02 09:05:06
品牌 Logo 应用领域
联笙电子 - AMICC 动态存储器
页数 文件大小 规格书
41页 865K
描述
2M X 16 Bit X 4 Banks Synchronous DRAM

A43L3616V-7V 技术参数

是否Rohs认证: 符合生命周期:Contact Manufacturer
包装说明:TSOP2, TSOP54,.46,32Reach Compliance Code:unknown
风险等级:5.48访问模式:FOUR BANK PAGE BURST
最长访问时间:5.4 ns其他特性:AUTO/SELF REFRESH
最大时钟频率 (fCLK):143 MHzI/O 类型:COMMON
交错的突发长度:1,2,4,8JESD-30 代码:R-PDSO-G54
长度:22.22 mm内存密度:134217728 bit
内存集成电路类型:SYNCHRONOUS DRAM内存宽度:16
功能数量:1端口数量:1
端子数量:54字数:8388608 words
字数代码:8000000工作模式:SYNCHRONOUS
最高工作温度:70 °C最低工作温度:
组织:8MX16输出特性:3-STATE
封装主体材料:PLASTIC/EPOXY封装代码:TSOP2
封装等效代码:TSOP54,.46,32封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE电源:3.3 V
认证状态:Not Qualified刷新周期:4096
座面最大高度:1.2 mm自我刷新:YES
连续突发长度:1,2,4,8,FP最大待机电流:0.001 A
子类别:DRAMs最大压摆率:0.16 mA
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):3 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子形式:GULL WING端子节距:0.8 mm
端子位置:DUAL宽度:10.16 mm
Base Number Matches:1

A43L3616V-7V 数据手册

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A43L3616  
Pin Descriptions  
Symbol  
Name  
Description  
CLK  
CS  
System Clock  
Chip Select  
Active on the positive going edge to sample all inputs.  
Disables or Enables device operation by masking or enabling all inputs except  
CLK, CKE and L(U)DQM  
Masks system clock to freeze operation from the next clock cycle.  
CKE should be enabled at least one clock + tss prior to new command.  
Disable input buffers for power down in standby.  
CKE  
Clock Enable  
Row / Column addresses are multiplexed on the same pins.  
Row address : RA0~RA11, Column address: CA0~CA8  
Selects bank to be activated during row address latch time.  
Selects band for read/write during column address latch time.  
A0~A11  
Address  
BS0, BS1  
Bank Select Address  
Latches row addresses on the positive going edge of the CLK with RAS low.  
Enables row access & precharge.  
Row Address Strobe  
RAS  
CAS  
Latches column addresses on the positive going edge of the CLK with CAS low.  
Enables column access.  
Column Address  
Strobe  
Write Enable  
Enables write operation and Row precharge.  
WE  
Makes data output Hi-Z, t SHZ after the clock and masks the output.  
Blocks data input when L(U)DQM active.  
Data Input/Output  
Mask  
L(U)DQM  
DQ0-15  
Data Input/Output  
Data inputs/outputs are multiplexed on the same pins.  
Power  
Supply/Ground  
VDD/VSS  
Power Supply: +3.3V±0.3V/Ground  
Data Output  
Power/Ground  
VDDQ/VSSQ  
NC/RFU  
Provide isolated Power/Ground to DQs for improved noise immunity.  
No Connection  
(February, 2002, Version 3.0)  
3
AMIC Technology, Inc.  

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