A43L1632A
Operating AC Parameter
(AC operating conditions unless otherwise noted)
Version
Symbol
Parameter
Unit
Note
-5
-5.5
-6
-7
tRRD(min)
tRCD(min)
Row active to row active delay
2
CLK
CLK
1
1
3
3
3
3
RAS to
delay
CAS
tRP(min)
tRAS(min)
tRAS(max)
tRC(min)
Row precharge time
Row active time
3
8
3
7
3
7
3
7
CLK
CLK
μs
1
1
100
Row cycle time
11
10
10
10
CLK
1
tRDL(min)
tCDL(min)
tBDL(min)
tCCD(min)
Last data in to row precharge
Last data in to new col. Address delay
Last data in to burst stop
2
1
1
1
2
1
CLK
CLK
CLK
CLK
2
2
2
3
Col. Address to col. address delay
CAS Latency = 3
CAS Latency = 2
Number of valid output
data
ea
4
Note: 1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and
then rounding off to the next higher integer.
2. Minimum delay is required to complete write.
3. All parts allow every cycle column address change.
4. In case of row precharge interrupt, auto precharge and read burst stop.
PRELIMINARY (March, 2007, Version 0.0)
9
AMIC Technology, Corp.