Datasheet > A43L0632G-95I

A43L0632G-95I

更新时间： 2022-04-25 03:52:36

品牌	Logo	应用领域
联笙电子 - AMICC		动态存储器
页数	文件大小	规格书
42页	502K
描述
1M X 16 Bit X 4 Banks Synchronous DRAM

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A43L0632G-95I 数据手册

A43L2616B

Mode Register Filed Table to Program Modes

Address

BA0, BA1

A11, A10

Function

RFU

W.B.L

CAS Latency

Burst Length

(Note 1)

(Note 2)

Test Mode

Type

CAS Latency

A6 A5 A4 Latency

Burst Type

Burst Length

A8 A7

Type

A2 A1 A0

BT=0

BT=1

Mode Register Set

Reserved

Sequential

Interleave

Vendor

Use

Only

Reserved

Reserved Reserved

256(Full) Reserved

Write Burst Length

Length

Burst

Single Bit

Power Up Sequence

1. Apply power and start clock, Attempt to maintain CKE = “H”, DQM = “H” and the other pins are NOP condition at inputs.

2. Maintain stable power, stable clock and NOP input condition for a minimum of 200μs.

3. Issue precharge commands for all banks of the devices.

4. Issue 2 or more auto-refresh commands.

5. Issue a mode register set command to initialize the mode register.

cf.) Sequence of 4 & 5 may be changed.

The device is now ready for normal operation.

Note : 1. RFU(Reserved for Future Use) should stay “0” during MRS cycle.

2. If A9 is high during MRS cycle, “Burst Read Single Bit Write” function will be enabled.

(December, 2009, Version 1.3)

AMIC Technology, Corp.

1...7 8 91011 12 13...42

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