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A43L0632G-7F PDF预览

A43L0632G-7F

更新时间: 2024-01-12 04:51:16
品牌 Logo 应用领域
联笙电子 - AMICC 动态存储器
页数 文件大小 规格书
44页 1305K
描述
512K X 32 Bit X 2 Banks Synchronous DRAM

A43L0632G-7F 技术参数

生命周期:Contact Manufacturer包装说明:,
Reach Compliance Code:unknown风险等级:5.75
Base Number Matches:1

A43L0632G-7F 数据手册

 浏览型号A43L0632G-7F的Datasheet PDF文件第5页浏览型号A43L0632G-7F的Datasheet PDF文件第6页浏览型号A43L0632G-7F的Datasheet PDF文件第7页浏览型号A43L0632G-7F的Datasheet PDF文件第9页浏览型号A43L0632G-7F的Datasheet PDF文件第10页浏览型号A43L0632G-7F的Datasheet PDF文件第11页 
A43L0632  
Operating AC Parameter  
(AC operating conditions unless otherwise noted)  
Version  
Symbol  
Parameter  
Unit  
Note  
-6  
12  
18  
-7  
14  
20  
tRRD(min)  
tRCD(min)  
Row active to row active delay  
ns  
ns  
1
1
RAS to  
delay  
CAS  
tRP(min)  
tRAS(min)  
tRAS(max)  
tRC(min)  
Row precharge time  
Row active time  
18  
42  
20  
49  
ns  
ns  
µs  
ns  
1
1
100  
60  
100  
68  
Row cycle time  
1
tCDL(min)  
tRDL(min)  
tBDL(min)  
tCCD(min)  
Last data in new col. Address delay  
Last data in row precharge  
1
2
1
1
CLK  
CLK  
CLK  
CLK  
2
2
2
Last data in to burst stop  
Col. Address to col. Address delay  
Note: 1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and  
then rounding off to the next higher integer.  
2. Minimum delay is required to complete write.  
PRELIMINARY (August, 2005, Version 0.0)  
7
AMIC Technology, Corp.  

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